Van der Waals: One Memory, Three Ways onto a GPU

#1Why memory needs a new shape

Open the lid on a 2026 AI accelerator and the memory sits in rectangles around the processor. NVIDIA's Rubin GPU joins two reticle-sized compute dies and carries up to 288 GB of HBM4 at up to 22 TB/s [11], in eight 36 GB stacks [12]. Each compute die's share, 144 GB and 11 TB/s, is this paper's yardstick (NVIDIA's NVL72 page lists 19.2 TB/s per GPU, 9.6 per die [11]). Each stack is a base die with twelve or sixteen thinned DRAM dies, drilled with TSVs and bonded one onto the next. More of the work these parts do asks for capacity near the processor as much as for bandwidth: long-context key-value caches, the idle experts of a mixture-of-experts model, large serving batches.

Why it matters. Four reasons, each physical:

• Heat has a short path. A Side die's 48 tiers are 16.8 µm of memory with no bonded joint between them, so the memory runs within 0.5–1.0 K of its base (§11); an HBM stack puts twelve or sixteen thinned dies, and as many bump-and-underfill joints, in the same heat path.
• Thin, with no stacking ceiling. Each tier adds 0.35 µm and nothing is drilled, bumped or thinned per tier. HBM stops at sixteen dies under a 775 µm package height; here the count is set by the growth's anneal budget, about 300 tiers with W/Ru base wiring (§6), and 300 tiers would stand 105 µm tall.
• Less energy per bit. Bond moves a bit from cell to GPU receiver for 0.08–0.4 pJ before the base datapath, 6 to 48 times less than HBM4's 2.4–4 pJ, because the data crosses one bond instead of two PHYs and an interposer (§15); Grown's cell-to-GPU figure is 0.03 pJ with its tier-P latch, receivers and ECC excluded (§20).
• Little for a cosmic ray to hit. The channel is one atomic layer of MoS₂ and the bit sits on a transistor gate, not in a trench capacitor, so a particle strike has almost no volume to deposit charge in. The soft-error rate that leaves is untested: no Van der Waals part has been irradiated.

The HBM4 standard, JESD270-4, defines stacks 4, 8, 12 or 16 dies high, built from 24 Gb or 32 Gb dies, with a 2048-bit interface at up to 8 Gb/s per pin. Its largest density is 64 GB, sixteen 32 Gb dies [13]; shipping parts sit below that. Samsung began commercial HBM4 shipments on 12 February 2026 at 11.7 Gb/s and up to 3.3 TB/s per stack, 12-high at 24–36 GB [14]. Micron's 36 GB 12-high part, above 2.8 TB/s, has shipped in volume since the first quarter of 2026 [15]. SK hynix showed a 16-high 48 GB stack at CES 2026, its DRAM dies reportedly thinned to 30 µm for the package height [16].

HBM5. HBM5 is unpublished: JEDEC lists it as in development (October 2026) [102], and what is public does not agree on its width or speed, so Side's port shape is provisional (§10); Bond and Grown are compared with HBM4, which ships today.

Height. HBM was 720 µm tall through HBM3E and is 775 µm for 12- and 16-high HBM4 [17]. JEDEC is reportedly weighing about 900 µm for HBM4E (rumor, April 2026) [17], and 900–1,000 µm for 20-high HBM5 (rumor, July 2026) [18]. SK hynix has said hybrid bonding becomes essential at 20-layer stacks (vendor-announced, 17 April 2025) [26], and does not expect it to be ready for HBM4E, which leaves HBM5 as the earliest slot (vendor-announced, 23 August 2026) [19]; Samsung and SK hynix had already pushed it past HBM4 [18]. Each added layer of capacity is bought with a thinner die, another bonded interface or a taller package.

Energy. Every bit read from HBM crosses two PHYs and millimetres of interposer. NVIDIA's chief scientist puts HBM4 at about 3–4 pJ per bit [20], and d-Matrix, at Hot Chips 2026, put HBM4 at about 2–3 pJ per bit, with 2.4 used in coverage of the talk [21]; both figures reach us second-hand. At Rubin's 22 TB/s, 2.4–4 pJ per bit is 422–704 W of memory traffic (Eq. 45).

Supply. HBM3E takes about three times the wafer input of DDR5 per bit, and Micron expects that ratio to rise [22]. By the end of 2026 HBM is expected to take about 22% of DRAM wafer input for about 9% of the bits, customers reportedly receive 60–70% of the HBM4 they order, and the shortage is expected to run into 2027 [23]. Roadmaps add capacity per stack slowly: KAIST's TERA Lab projects 48 GB for HBM4E (2028), 80 GB for HBM5 (2029), 120 GB for HBM6 (2032) and 192 GB for HBM7 (2035) (analyst or roadmap, June 2025) [24][103].

The incumbents are moving memory closer. Samsung's custom-HBM roadmap ends with DRAM stacked on the processor, zHBM [25]. SK hynix has described '3D HBM' stacked on the GPU from HBM5, with no date (vendor-announced, 17 April 2025) [26]. d-Matrix showed its accelerator die bonded onto a custom DRAM die at Hot Chips 2026, with figures it calls projections from early silicon [21]. imec simulated HBM stacked on a GPU and found a 141.7 °C peak before mitigation [27]. None of them has announced a volume date for DRAM on a GPU.

Van der Waals grows the memory as tiers on a base instead of stacking finished dies. Side's 48 tiers add 16.8 µm, about half of one of HBM4's 30 µm dies. The tiers can be grown on any back end that tolerates the process, so the same memory can reach a GPU three ways (Figure 1).

#Three ways onto a GPU

Side puts the tiers on PhantaField's own silicon base die (28 nm in the cost basis; a finer node is a cost decision, not a tier redesign) and ships one die for an HBM5-class site beside the GPU on the interposer. The GPU needs an HBM5-class controller and PHY that support its 64 GB density (§10). A bad Van der Waals never costs a GPU. It is sold on capacity per site from one tested die, not on speed.

Bond puts six Van der Waals tiles under each GPU compute die. Each tile is a tested 126 mm² die on Side's outline; two by three, with narrow filled gaps, they cover 94.5% of the GPU's face. Their tiers grow face-up on silicon bases and are hybrid-bonded to the GPU's front; the GPU's silicon back faces the cold plate. Vias through each tile carry all the GPU's power and I/O down to the package; the gaps and edge band hold only fill. The data crosses one bond, so the port is wide and cheap per bit. A 126 mm² tile yields far better than one memory die the size of the GPU (§16). The GPU keeps its heat path, but the memory's own heat crosses the GPU.

Grown drops the base die. The GPU maker's foundry grows the tiers on the finished GPU wafer, between its last metal and its bumps, and PhantaField supplies the process, the growth tools and a design kit. Nothing crosses a bond or a PHY, and on a front-side-powered GPU the tiers sit on the package side, out of the main heat path. With no base die and no seal rings or gaps, 46 data tiers, the same as Bond's, hold 416 GB against Bond's 352 with 20% more sense paths: more than Bond at the same memory temperature, row cycle and cell retention, with lanes above 119 MHz (§20). In exchange, our chemistry runs inside a leading-edge GPU line, 49 tiers deep, on untested GPUs.

#2The cell

Each bit is a two-transistor, zero-capacitor (2T0C) gain cell (Figure 2). A write transistor, gated by the write wordline (WWL), connects the write bitline (WBL) to a storage node Q. A read transistor has Q as its gate, its source on the read wordline (RWL) and its drain on the read bitline (RBL) [1]. A row is read by pulling its RWL low while the unselected RWLs are held at the RBL precharge level, so only the selected row's cells can conduct. There is no capacitor: the bit is the charge on the read transistor's gate, read by sensing how much current that transistor passes. The read does not use the charge up, so, unlike a 1T1C cell, nothing is written back after a read.

That is why the cell suits a stack: a 1T1C cell keeps its bit on a capacitor etched deep into silicon; the gain cell has no capacitor and no deep trench, so it can be made at low temperature over finished wiring, tier after tier. In the design basis both transistors are MoS₂ nFETs, the cell occupies 8F² (6,272 nm² at 28 nm) and stores one bit, the array rail is 0.6 V, a read costs 30 fJ per bit and a write 20 fJ per bit [1]. Its footprint is larger than a commodity cell's 6F², which Van der Waals pays back in height.

#What has been measured

Two measured results bear on Van der Waals [2]: the capacitor-less 2T0C cell (a MoS₂ write FET over a silicon read FET) stays readable past 1,000 s and shows about five distinct levels; MoS₂ nFETs have been measured in a stack over a silicon p-FinFET.

Neither result is a Van der Waals tier. In every format each tier sits over a finished back end: PhantaField's base die for Side and Bond, the GPU's own wiring for Grown. No tier can use a silicon read transistor, so every tier needs a cell in which both transistors are MoS₂, and that cell has not yet been measured. The retention result also cannot be credited to the design: it states no temperature and was not taken at the 0.6 V design rail. Section 3 uses the design retention, which is far shorter.

#Prior art

The measured cell is in line with the published literature, not ahead of it, and we make no novelty claim on it. Fudan University published the same topology, a MoS₂ write transistor with a silicon read transistor, in 2024 [28]. Oxide-channel 2T0C cells report the longest retention we could verify (table), and high-temperature results exist for IGZO (imec at 95 °C; Peking University, 7 ks at 85 °C, as cited by imec) and for SEL's oxide-semiconductor DRAM (over 99% of data retained after 1 h at 85 °C) [29][30][31][88]. CXMT, a DRAM maker, co-authors MoS₂ gain-cell work with Fudan and Shaoxin Laboratory, including a 2026 cell reported as quasi-non-volatile with a retention value we have not verified [32][33].

Apart from imec's 95 °C result, the papers in the table state no test temperature, so they cannot be set against DRAM refresh windows. Because every Van der Waals tier uses only n-type transistors, an oxide channel such as IGZO is the closest alternative to MoS₂, and imec already presents IGZO 2T0C as a back-end memory on logic [29]. Whether a 2D channel is the better choice for nFET-only tiers is open; the data that would settle it are drive current per tier at a rail of 1 V or less, retention at 85–105 °C, and the thermal budget each channel needs (§24). What Van der Waals adds is a design: tiers grown on the NanoGalaxy PP-MOCVD tool (§6), stacked to tens of tiers and defined three ways for a GPU. Others have grown MoS₂ on CMOS and built monolithic memory on logic (§6, §23).

#3Retention, refresh and temperature

A gain cell leaks: Q drains slowly through the write transistor's off-state, so every bit must be rewritten before it fades below the sense threshold. The design basis sets retention at 1.8 s at 25 °C and halves it every 10 °C [1] (Eq. 3):

τ(T) = 1.8 s × 2^(−(T − 25)/10)
     = 1.8 s at 25 °C · 28.1 ms at 85 °C · 14.1 ms at 95 °C · 7.0 ms at 105 °C
refresh interval = 1 s · 20 ms (1.4× margin) · 10 ms · 5 ms

Thermal sensors next to the array set the interval (Figure 3A). A refresh is a read followed by a write-back, so we charge it 30 + 20 = 50 fJ per bit. Over 8×10⁹ bits per GB, 50 fJ is 0.4 mW per GB for each refresh per second (Eq. 4). Only data tiers are refreshed, including their ECC bits and spare columns; unused spare tiers are not. The per-GB figures differ only by each format's ratio of refreshed raw GB to GB sold (1.15–1.25), Side's being highest (§9).

HBM's 23–52 mW per GB states no temperature, and self-refresh slows on a cool die, so the 25 °C figure cannot be set against it. At 85 °C refresh costs what HBM's self-refresh does; at 105 °C about twice HBM's top figure. DDR5 refreshes within a 32 ms window up to 85 °C and doubles its rate from 85 to 95 °C [36]; Van der Waals refreshes 31× less often at 25 °C and 1.6× more often at 85 °C. At 105 °C our 5 ms interval is no better than a 1T1C DRAM's: d-Matrix reports 4 ms at 105 °C for its custom DRAM [21].

The low-refresh case holds only for a cool die, and none of the three formats runs cool: Side at whatever temperature its HBM site runs, Grown up to about 3 K above the GPU junction, Bond a few K above it. The junction temperature a GPU maker guarantees under the memory decides the bill: 85 °C against 105 °C is 4× in refresh power.

Refresh also occupies the sense array. A refresh read takes a sense path from host reads; the share is the refresh duty (Eq. 5):

duty = data tiers × bits per sense path per tier × f × row cycle
bits per sense path per tier = 110.0×10⁶ / (sense paths per mm²) = 4,097 at 16:1 (Side) · 2,049 at 8:1 (Bond, Grown)
S64  at 105 °C, 20 ns row cycle: 46 × 4,097 × 200 × 2×10⁻⁸ = 75.4%
B352 at 105 °C, 20 ns row cycle: 46 × 2,049 × 200 × 2×10⁻⁸ = 37.7%
G416 at 105 °C, 20 ns row cycle: 46 × 2,049 × 200 × 2×10⁻⁸ = 37.7%  (the same 46 data tiers as B352)

The row cycle has not been measured, and every duty scales with it. Each format is rated by its own rule, always printed with its row cycle, and the rating is a memory temperature. Side is rated where, after refresh, the array still feeds the port: what is left reads every stored bit, ECC and spares included, at full access efficiency, with a 1.11–1.13× margin at 105 °C and 20 ns. Bond and Grown are rated where refresh takes no more than half the array (refresh duty 50% or less); what that leaves Bond's port is in §15. Side's S64 is on a 16:1 array; Bond and Grown use an 8:1 array, which doubles the sense paths and halves every duty (ratings: §11, §16, §20). Hot operation is the reason for 8:1: at 16:1, the 46 data tiers of B352 and G416 would take 75.4% of the array at 105 °C and 20 ns and 151% at 40 ns, so neither could be rated at GPU temperature.

How much margin the intervals carry. The intervals are sized to one design cell's τ, not to the weak-bit tail of an array that holds more than 10¹² bits per GPU die. They sit at 56% of τ at 25 °C and 71% at 85–105 °C. At the 1 s point a stored 1 already leaves only 15–35 mV of read overdrive in circuit simulation, so the hot intervals leave less. A weak bit late in its interval also gives less read current, so the row cycle near the end of an interval may exceed 40 ns; the 40 ns case is not a worst case. If the tail forces refresh twice as often, refresh costs about 1.0, 46–50, 92–100 and 184–199 mW per GB at 25, 85, 95 and 105 °C, and the ratings move (Eq. 5):

#4The memory tier

Each tier is a full-footprint DRAM array at the planar density of the Sophon design basis [1] (Eq. 1, Eq. 2). The tiers' 2D TMD devices use 28 nm design rules, whatever node lies beneath them (§6). With an 8F² cell at F = 28 nm, a 45% periphery allowance and one bit per cell:

D = 10¹² / (8 × 28² × 1.45) = 10¹² / 9,094.4 nm² = 110.0 Mb/mm² per tier
user fraction = (64/72 SECDED) × (256/260 spare columns) = 0.8752
Side  (126 mm² die):            110.0 × 126 / 8,000        = 1.7325 GB raw → 1.5163 user
Bond  (six 126 mm² tiles, 15.3% reserve): 110.0 × 640.4 / 8,000 = 8.805 GB raw → 7.7064 user
Grown (800 mm² die, 4% field):  110.0 × 800 × 0.96 / 8,000 = 10.56 GB raw  → 9.2423 user

Per tier, this is not dense. One tier holds 0.110 Gb/mm², 25% of Samsung's 1b LPDDR5X die at 0.436 Gb/mm², and below older 16 Gb DDR5 dies at 0.21–0.24 Gb/mm² [37]. Van der Waals wins only by height.

What a tier carries. Each tier carries only n-type MoS₂ transistors: the cells; tier-select and mat-select pass gates; a column multiplexer; bootstrapped nMOS write- and read-wordline drivers; and landings for the vertical vias. No sense amplifier, p-type transistor or logic sits on a tier. That keeps each tier to one MoS₂ growth pass, by our estimate, and independent of p-type 2D transistors, which have not yet reached the switching slope the design assumes.

Mats and the column multiplexer. A tier is divided into mats of 256 rows by 256 columns plus 4 spare columns, about 596 µm² each including its share of periphery, or 1,678 mats per mm². Side multiplexes 16 columns onto each global bitline (16 per mat, 26,848 per mm²); Bond and Grown multiplex 8 (32 per mat, 53,696 per mm²), because hot operation needs the sense paths (§3).

One tier design. Every tier in a stack is built from the same layout and answers only to its own enable (concept level). The tier design and process module are the same in all three formats, so tier learning carries across. The masks are set per footprint: Side's 126 mm² die with a 16:1 multiplexer; Bond's 126 mm² tile, on Side's outline, with an 8:1 multiplexer and openings for vias that follow one host GPU's pad plan, so Bond needs its own bitline, tower and via-opening masks per host; and Grown's GPU-sized tier with an 8:1 multiplexer and a 4% tower field.

The open question. The 45% periphery allowance was set for Sophon, where the sense amplifiers sit on separate logic tiers; Van der Waals moves them off the memory tiers but adds tier-select gates and tower keep-outs to every tier. Whether 45% still covers that, and so whether 110.0 Mb/mm² holds, is open until a tier is laid out (§24).

#5Going vertical

With no sense amplifiers on the memory tiers, every bit read travels vertically to a sense amplifier: to the base die in Side and Bond, to the periphery tier in Grown. Above each mat, global bitlines run as stacked monolithic inter-tier vias (MIVs) straight through the tiers. A 90 nm MIV grid has 1.235×10⁸ slots per mm² (imec's sequential-integration work, as used in [1]). The global bitlines take 26,848 (Side) or 53,696 (Bond, Grown) of them per mm², 0.02–0.043%. Against a 6 µm hybrid-bond grid's 27,778 sites per mm², the MIV grid is 4,444× denser. That density is inside the stack, not at the port: Grown's 4.12 M lanes, about 5,370 per mm², would fit in about 19% of a 6 µm bond face's sites, so a bonded port's width is a design choice (§20).

Only one tier in a mat column drives its global bitline at a time, as in 3D NAND. Each global bitline also carries the off-state leakage, and the drain overlap and fringe capacitance, of every unselected tier-select gate, up to 47 of them in a B352 tile, each fronting a local bitline of 256 read transistors. At an assumed 0.1 µA read current, holding that leakage to 10% of the signal needs about 210 pA per unselected gate at 105 °C in S64, a B352 tile and G416, with 48 memory tiers each (G416 adds tier P; Eq. 6). Read margin on a shared global bitline falls with tier count; it is not yet modeled (§24). If a via's capacitance per µm equals a minimum-pitch wire's 0.155 fF/µm, the vertical run adds 3–14% of the cell's read energy: least in Side, most in B352 (down its tiers, then up a data tower to the bond), G416 between (up to tier P, then down its lanes; Eq. 6, Eq. 33), before the unselected tier-select gates' overlap and fringe capacitance.

Towers. Power and I/O cross the stack in towers of parallel vias. In Side and Grown their wiring is tungsten or ruthenium, to survive the thermal steps of the tiers grown above them; Bond's vias are solid copper, made after the last tier, and see no tier step (§14). The load differs by format:

• Side carries only its own supply and its HBM5-class signals. At 105 °C that is at least 17.5–58 A (15.7 W at 0.9 V to 40.3 W at 0.7 V, before base logic and leakage), which needs about 0.018–0.059 mm² of tungsten via array at 19.6% fill, under 0.05% of the die, plus about 4,096 data towers and more for command, address, clock and sideband (Eq. 18). With the stack facing the interposer, every bump of the site's ballout needs a tower through all 48 tiers; SK hynix's HBM4 base has 16,148 micro-bumps [53]. This sits inside Eq. 1's unverified 45% periphery share; Side reserves no separate field.
• Bond reserves 15.3% of each tile for its vias, their keep-outs and the seal ring. All the GPU's supply current and I/O climb through the tiles' vias to the bond; current over the fill-only gaps and band moves sideways in the GPU's grid to the nearest tile (§14).
• Grown reserves 4% of every tier as a tower field. The GPU's own power, ground and I/O climb through it to bumps rebuilt on top of the stack, beside the memory's own rails (§20).

The industry's 4F² DRAM work also puts the periphery under the array: Samsung's cell-on-peripheral DRAM at ISSCC 2026 and SK hynix's circuit-under-cell platform, by wafer bonding, at VLSI 2025 [38][39]. Here one periphery layer serves many tiers instead of one.

#6Growing the tiers

Every tier is grown with the NanoGalaxy PP-MOCVD tool, which grows 2D films below 450 °C on 300 mm wafers [3]. Whether that temperature is safe depends on what the tiers are grown on.

On a base PhantaField specifies (Side, Bond). The tiers grow on our own silicon base (28 nm in the cost basis; a finer node is a cost decision, not a tier redesign, if its back end meets the tier budget below). The design basis assumes tungsten or ruthenium wiring in that back end, and the Sophon design's anneal limit of about 300 tiers rests on that assumption [1]. If the base instead uses a standard copper/low-k back end, Side and Bond face the same ≤400 °C-class requirement as Grown. Which metal the base uses is still to be decided (§24).

On the GPU's back end (Grown). The tiers grow on a finished copper/low-k back end, which the literature conventionally holds below about 400 °C [40]; older monolithic-3D design work assumes under 450 °C over a copper back end [41]. No foundry publishes a time-at-temperature budget for N3, N2 or A16; TSMC's A16 paper at VLSI 2026, as covered publicly, gives none [42]. So for Grown, '≤400 °C class' is a requirement the module must meet, not a capability we have shown. Every tier step counts against it: growth, gate and dielectric deposition, contacts, via fill and any anneal.

Exposure adds up. The only public anchor we found for time at temperature on a finished back end is analyst wording that an embedded MRAM module in Intel's 22FFL must survive about an hour above 400 °C after it is formed [44]. A 49-tier Grown stack puts many more thermal steps on the host than one MRAM module does. Whether G416 exceeds that hour turns on where its growth runs against 400 °C (two cases, §19). Tier counts elsewhere do not transfer: Bond's 48 tiers grow on its own tiles, and Sophon's 64 tiers are a published design target, not a demonstrated stack [1]. IBM re-checked its host back end's electromigration and dielectric breakdown after embedding MRAM in 14 nm logic [45], and Grown's host will need the same. Others have shown the direction is possible: MIT and ORNL grew monolayer MoS₂ below 300 °C in 60 minutes or less on 200 mm CMOS wafers [40], with another group's tool, and CEA-Leti has processed top-tier transistors over copper/ultra-low-k wiring [46]. That is prior art and evidence of feasibility, not data about our tiers.

The first gate. Before any tier goes on a GPU, a thermal-history twin for each format: full-flow logic wafers taken through every tier's steps in the real growth ambient, then re-checked (§25).

#7Yield and repair

Yield has two parts: the silicon the tiers are grown on, and the tiers. The silicon follows the design basis's yield model at its defect density, D₀ = 0.1/cm² [1]: 88.28% for a 126 mm² die (Side's die, Bond's tile) and 47.38% for the 800 mm² die Grown assumes (Eq. 7). Each tier is taken to survive with probability 0.997, imec's process-control figure for monolithic 3D as used in [1]. It is an assumption, not our measurement, and a stack of N tiers yields 0.997^N (Eq. 8).

A note on tier area. We apply 0.997 per tier whatever the tier's area; 0.997 was set at 126 mm², Side's die and Bond's tile. That implies a tier-killing defect density of 2.4×10⁻³/cm² there and 3.8×10⁻⁴/cm² on an 800 mm² Grown tier, 6.3× apart; the Sophon basis, a 750 mm² tier, is 4.0×10⁻⁴/cm². Scaled by area from that basis, a 126 mm² tier would yield 0.9995 and an 800 mm² tier 0.9968, so 0.997 is conservative for Side and for Bond's tiles. For Grown the check is circular, because the Sophon figure rests on the same imec assumption; scaled by area from 126 mm² an 800 mm² tier yields about 0.981, and one carrying 5–8 patterning levels may do much worse (§16, §20). A memory die with the GPU's outline would share that question, which is one reason Bond is split into 126 mm² tiles (§16).

Spare tiers need isolation. With two spare tiers, a stack keeps full capacity when no more than two tiers fail: P(≤2 of 48 fail) = 0.99958 at 0.997 per tier for S64's 48 tiers, each B352 tile's 48 and G416's 48 below tier P. That needs tier isolation, switching a failed tier out electrically and a spare in, which is unproven in every format. A short on a shared vertical line or rail reaches every tier in that column and is fatal either way.

The rest of the repair stack. Four spare columns per 256 repair faults on a single local bitline. They do not repair the dominant monolithic-3D defect, an open in a vertical via [1], once that via is a global bitline: it carries 8 (Bond, Grown) or 16 (Side) columns of every mat it serves, an open cuts all of them in every tier beyond it, and 260 columns do not divide into whole global bitlines at either ratio. Such an open is absorbed by on-die SECDED (72,64), with one global bitline's columns interleaved across words, which spends correction headroom that retention and soft errors also need, or by mapping out the mat. Spare global bitlines would repair it properly, at a cost in user fraction not yet carried here (§24). Scrubbing on refresh and capacity bins catch what remains. Per-tier yield below 0.997 raises every format's cost (§11, §16, Risk 9). Repair matters most on Grown's GPU-size tiers (§20); on Bond's tiles, per-tier yield moves B352's cost (§16).

How a bad tier reaches the GPU (Figure 4A):

#8Cost method

All three formats use the cost equation of [1]: wafer cost over gross dies, divided by yield (Eq. 9). A silicon base wafer, 28 nm in the cost basis (§6), costs $3,500. Each tier adds $3,600 per wafer; in the design basis about $600 of that is the growth pass and anneal, the rest patterning, with no mask count behind it (§24). A 300 mm wafer holds 501 gross dies of 126 mm² and 64 of 800 mm². Side adds a fixed $85 per die ($60 package plus $25 test, from [1]), standing in for bumping, test and burn-in. Bond adds the same $85 per tile as test only, and seven unsourced tier-equivalents: two on its tile wafer, for the through-stack vias and the bond layer, and five on the GPU wafer, charged per sort-good GPU, for bonding the tiles, the gap fill, thinning, the backside rail vias, and the backside wiring and bumps. Burn-in is left to the GPU maker. Grown adds no fixed amount; its tiers are grown on every GPU site, so its cost per good GPU divides by the GPU's own yield.

Cost is not price. The October 2026 market is at a cyclical peak: conventional DRAM contract prices rose 93–98% quarter on quarter in the first quarter of 2026 alone [47], and DDR5 spot sits above HBM3E contract, because HBM is priced under annual agreements [23][48].

The family finding. Per GB sold, S64 costs $8.52, B352 $10.62 per set of six tiles and G416 $8.28–8.45 per good GPU at a GPU yield of 0.8 (Eq. 11). The last two divide by different yields, Bond's by its tiles' and Grown's by the GPU's, so they do not rank the two. With tier isolation, B352 costs $9.58 at its tiles' isolated yield and G416 $13.98–14.27 at the 47% Murphy yield of an 800 mm² die. The tier adder dominates Side and Grown, which sit at about 3.8–3.9× the crude commodity cost proxy and about 1.3× the HBM cost proxy. Bond is 1.6× the HBM cost proxy: its 126 mm² tiles yield 88% before their tiers, as Side's die does, against 47% for a GPU-size memory die, but it carries seven tier-equivalents for its bond, fill and backside steps, and the 15.3% of each tile given to vias leaves a tile 58.7 GB where Side's die, on the same outline, holds 64 (§9). The format moves cost and risk around; it does not make bits cheaper. Pitched on dollars per GB against DIMMs, Van der Waals would be underwater in the next downturn; its case against HBM rests on capacity, bandwidth per GB and supply, not on cost.

What each cost leaves out. Side excludes CoWoS assembly. Bond excludes the per-host mask sets, the GPU maker's burn-in, a hot retention re-screen after bonding and the GPUs scrapped by failed stacks; with those GPUs it is $13.03–35.56 per GB sold per good stack (§16). Grown excludes the GPU-side area for lane receivers and channel controllers, any GPU lost to a GPU-fatal tier defect, and the fab time its added mask levels take (§20).

#9Side in one picture

Van der Waals Side is one die (Figure 5). Its silicon base (28 nm in the cost basis; a finer node is a cost decision, not a tier redesign) carries all the logic a DRAM needs (§10). On the base's interconnect we grow identical tiers at 28 nm design rules and join them to the base with MIVs. Side is memory only; the GPU does all the computing (§17).

The site. No HBM5 footprint has been published as of 18 October 2026 [102], and HBM4's is reported three ways: 10.5 × 12.0 mm (126 mm²; rumor, January 2026) [52], 12.4 × 11 and 12.8 × 11 mm (SK hynix, 23 August 2026) [53], and 11 × 12.8 mm (Samsung's HBM4 base die) [25]. We keep the die at 126 mm², the smallest. A site is a ballout, keep-outs, an underfill dam and a lid height, so S64 fits an HBM5 site only if it carries that site's whole bump map, and a 4,096-bit port roughly doubles the PHY's bump field (§10).

Orientation. The die mounts flip-chip, stack side down, on the site's interposer, as an HBM stack does; power and I/O reach the micro-bumps through towers across the stack. The base silicon faces the lid and cold plate, left about 700–750 µm thick, so the die reaches 775 µm, HBM4's limit as SK hynix states it [19]. HBM5's height is unpublished; 900–1,000 µm is reported under discussion (§1). In such a site a stepped lid or lid pedestal takes up the 125–225 µm; the die does not change. A device-free silicon spacer bonded to the base's back is the last resort: it adds a bond line in the heat path of the base, which carries the PHY, though still with no bonded memory die.

One part. Side is offered as S64 alone (table above); Bond and Grown count decimal GB, not binary (Appendix D). The same base die and mask set could stack more tiers; §11 shows why we do not.

The fallback. If IR drop or signal integrity through the stack proves unworkable (§24), the die flips: TSVs go into the base die only and the stack faces the lid. One TSV step in one die, still no die stacking; Side would then claim no stacked dies and no bonding, not 'no TSVs'.

#10Side's base die and interface

The silicon base die (28 nm in the cost basis; a finer node is a cost decision, not a tier redesign) holds everything that is not a cell:

• Global sense array. 3.38 million binary current-latch sense amplifiers, one per global bitline at a 16:1 column multiplexer, the Sophon sense-amplifier design [1], with precharge and write drivers beside them. Read time is set by how fast a sub-µA cell current develops the bitline, not by the latch, and is unmeasured.
• Wordline support. Charge pumps for the boosted write wordline (the boost level is not yet specified) and the row, column and tier decoders.
• Refresh engine. Distributed thermal sensors set the interval (§3).
• Error correction and RAS. On-die SECDED (72,64), with scrubbing on refresh, and an error log.
• Repair. E-fuse repair for 4 spare columns per 256 [1], a tier-disable map, and capacity bins for dies that lose tiers.
• Test. Memory BIST and burn-in hooks.
• Power. Regulation from the site's rails down to the 0.6 V array rail and the boost rail. HBM4's are VDDQ 0.7–0.9 V and VDDC 1.0–1.05 V [13]; HBM5's are unpublished.
• Interface. An HBM5-class PHY and protocol logic, 4,096 data bits wide, provisional (below).

At a 10 ns row cycle the sense array reads 3.38×10¹⁴ stored bits per second, 42 TB/s, about 10× S64's 4.1 TB/s; at 20 ns it is 21 TB/s. Hot refresh sizes this array (§3), and at 105 °C the port nearly uses what refresh leaves (§11). Whether all of it fits in 126 mm² at the 28 nm cost basis has not been checked with a floorplan. Samsung's 2,048-bit HBM4 PHY takes more than 8 × 4 mm of its 140.8 mm² base die [25]; at that density a 4,096-bit PHY's bump field would take about 64 mm², half of S64's die (derived). That floorplan is the first design gate; if the PHY does not fit, the die grows.

Organisation. The port is 64 channels of 2 pseudo-channels, 128 in all, until HBM5 defines its own. Each pseudo-channel owns 1/128 of the footprint, 0.98 mm², through all tiers, so capacity and refresh load spread evenly; banks are tier groups crossed with footprint regions. Address map, density bits and timing wait for the standard.

S64 presents an HBM5-class port, not a standard one. HBM5 is unpublished: JEDEC lists it as in development (October 2026) in its JC-42.2 subcommittee, with no width, pin rate, channel count, ballout, footprint, height, density bins, timing or refresh rules [102]. A draft exists but is not public: Synopsys described HBM5 verification IP built to 'JEDEC HBM5 Draft version 1.0-04' (vendor-announced, August 2026; the page has since been withdrawn) [119]. HBM4E is unpublished too [114]. The public indicators of HBM5's width conflict. KAIST's TERA Lab projects 4,096 data bits at 8 Gb/s per pin (analyst or roadmap, June 2025) [103], and one outlet reports a Samsung target of 4,096 bits at about 4 TB/s, which Samsung's own posts do not carry (rumor, August 2026) [106]. Synopsys's description of its draft-based IP gives QDR signalling, 64 pseudo-channels and close to 8 TB/s per stack [119], and one secondary report of it adds up to 32 Gb/s per pin and up to 32 channels (rumor, 31 August 2026) [121]. That reads as HBM4's 2,048-bit organisation at up to 32 Gb/s, 2,048 × 32 / 8 = 8.2 TB/s per stack (derived), though 4,096 bits at 16 Gb/s would give the same. S64's port follows KAIST's width: 4,096 × 8 / 8 = 4,096 GB/s, 4.1 TB/s per site (Eq. 15). If HBM5 keeps 2,048 bits at higher rates, or serialises as SPHBM4 does, S64's PHY, its 128-pseudo-channel map and its ballout change; the tiers do not. At the 28 nm cost basis no PHY approaches 32 Gb/s, so on such a port S64 would be a lower speed bin, if the standard allows one; run at 8.2 TB/s it would be rated 95 °C at 20 ns (Eq. 14). Until HBM5's timing is published, S64 is rated on throughput alone (§3, Eq. 14): whether its refresh duty (§11) can hide under HBM5's command timing cannot be shown. A refresh collision must never stall the host.

The fallback is the published standard. The same 48-tier die behind a 2,048-bit JESD270-4 port fills HBM4's largest density, 64 GB, a 16-high stack of 32 Gb dies [13]. It would fit HBM4 sites as an 8 Gb/s JESD270-4 bin, 2 TB/s per site, rated 105 °C at a 10 or 20 ns row cycle and 95 °C at 40 ns (Eq. 14), if its outline carries the site's ballout (§9) and its refresh hides under JESD270-4 timing, which is not shown: HBM4's REF and per-bank REFpb windows are fixed, with no wait or credit mechanism. Rubin's HBM4 sites run at about 10.7 Gb/s (22 TB/s over eight stacks) [11], so an 8 Gb/s part would be a slower bin than those use.

Bandwidth is the concession. S64's 4.1 TB/s per site (PHY target: 4,096 pins at 8 Gb/s) rests on KAIST's rate, likely stale: KAIST gave HBM4 8 Gb/s too [103], and shipping HBM4 runs 11.7 Gb/s [14]. A 2,048-bit HBM4E stack already carries about as much: Samsung's sample runs 3.6 TB/s, and 2,048 pins at 16 Gb/s give 4.1 TB/s (vendor-announced, May and June 2026; the 4.1 is derived) [109]. Samsung's latest statement, HBM5 at twice HBM4E's performance, does not say in what (vendor-announced, 1 September 2026) [120]. As stack bandwidth that is 7.2–8.2 TB/s, and S64 reaches 0.50–0.57× of it; as pin rate on 4,096 bits it is 32 Gb/s and 16.4 TB/s, and S64 0.25× (our inference). Samsung's earlier remark, an operating speed more than 50% above HBM4E (vendor-announced, 27 July 2026) [105], gives at least 5.4–6.1 TB/s by the stack reading (0.67–0.76×) and 12.3 TB/s by the pin reading (0.33×). KAIST's 4.0 TB/s and the reported Samsung 4 TB/s would read as parity, but both contradict Samsung's own statements; we claim none. We found no 28 nm HBM-class PHY. The fastest memory PHY IP listed for 28 nm is LPDDR4 at up to 4,267 Mb/s, a process-dependent top rate; IP listed only for 65–28 nm reaches 2,133 Mb/s [54]. On listed 28 nm IP, the cost basis, a 4,096-bit port gives 2.2 TB/s per site (1.09 on the slower IP), and even that assumes a ×16 or ×32 PHY's per-pin rate scales to 4,096 lanes. The evidence that 8 Gb/s is reachable at 28 nm is indirect: HBM3E runs 9.6 Gb/s from base dies in SK hynix's own DRAM process [55][56], and Intel ran UCIe-S at 48 Gb/s per lane on 22 nm [38]. Above about 9 Gb/s per pin the sense array, not the PHY, limits S64 at 105 °C and 20 ns (Eq. 14).

A finer base helps, but does not catch up. TSMC offers its 12 nm-class N12FFC+ and N5 nodes for HBM4 base dies [56], so a finer base for Side is a cost decision, not a tier redesign, if its back end meets the tier budget (§6). It would raise the pin rate: listed HBM3E PHY IP reaches 8.0 Gb/s per pin on TSMC N7 and 8.4 Gb/s on N5P (vendor-listed) [122], so a 7 nm-class base reaches the 8 Gb/s PHY target with listed IP, and HBM4E IP, the newest announced, runs 16 Gb/s on leading-edge nodes (vendor-announced, March and September 2026) [110]. But every HBM5 base die announced so far is leading-edge logic: Samsung's on its 2 nm GAA process (vendor-announced, 17 March and 27 July 2026) [105], and NVIDIA's own HBM base dies reportedly on TSMC 3 nm (rumor, 18 August 2025, restated for NVHBM on 18 October 2026 with no source named) [99][112]. A 7 or 12 nm-class base still trails them.

A later variant. JEDEC's SPHBM4 carries HBM4-class throughput on 512 data signals with 4:1 serialisation, on organic substrates with longer channels [57]. A Side variant on it could sit farther from the GPU and run cooler, cutting refresh power (§3). It needs host support, and a 4:1 serialising PHY is harder than a wide one at the 28 nm cost basis.

Power at 4.1 TB/s. The array reads 3.28×10¹³ user bits per second, 1.143 stored bits for each: 1.16 W. The PHY would cost 8.2–32.8 W at 0.25–1.0 pJ per bit, from UCIe's 0.25 pJ target [63] to a single-ended 28 nm interposer driver, an assumption (Eq. 16), and the dominant heat. The low end is aspirational: UCIe's figure assumes about 2 mm of reach on fine-pitch bumps at leading-edge nodes, not a driver at the 28 nm cost basis crossing millimetres of CoWoS interposer, so the 15.7 W site power and 17.5 A tower load built on it are optimistic. With refresh, the site draws 15.7–40.3 W at 105 °C before base logic and leakage. Hence no energy per bit and no multiple against HBM5 for Side.

What the GPU needs. S64 needs a GPU with:

• An HBM5-class controller and PHY. None exists: no HBM5 document, no announced PHY or controller IP [102][110].
• 4,096 data wires per site, if HBM5 is that wide, routed on the interposer, and about twice HBM4's PHY shoreline per site on the GPU die (§11).
• Support for a 64 GB density, a natural HBM5 bin only if HBM5 keeps HBM4E's 32 Gb dies, 16 high; with the 40 Gb dies KAIST projects [103] the bins would be 60 and 80 GB, and S64 would present an 80 GB map with 16 GB unbacked, which the host must know, or a 60 GB map giving up 4 GB.
• Timing and refresh rules that leave room for S64's internal refresh (above).
• Its own controller on our base, if it uses custom HBM. Custom HBM, as in NVIDIA's NVHBM, moves the memory controller into the HBM base die with a smaller custom PHY (vendor-announced, 26 August 2026) [111]. On S64 that controller would be built per customer on our base, at 28 nm area and power in the cost basis: not a drop-in.

Until HBM5 is published we claim neither compliance nor an unchanged GPU.

#11The Side part: S64

Why one part, and why this one. Side and Bond are chosen by one sequence of tests, in order, at the tiers' 28 nm design rules and the 28 nm cost basis; Grown shares the first and must also have more capacity and bandwidth than Bond (§20). First, rated 105 °C at a 20 ns row cycle on its format's criterion (§3, Eq. 14; on Bond's and Grown's half-array rule S64 would be a 95 °C part at 20 ns). Second, offerable on its own, needing no qualification beyond its first test vehicles. Third, the lowest modeled cost per GB sold among what is left (for Bond, at its fixed 48 tiers: §16); sizes within 2%, with and without tier isolation, are tied, and a tie goes to the part with more rating margin. Fourth, capacity breaks any tie left. The candidates were 70 tiers for 96 GB and 139 for 192 GB on the same base die and mask set (Figure 8). Behind the 4,096-bit port only S64 passes the first test: at 105 °C and a 20 ns row cycle its sense array is 75.4% busy and still keeps 5.20 TB/s of stored bits for the 4.61–4.68 TB/s the port needs, 1.11–1.13×; the 96 GB part would be 111% busy and the 192 GB part 223%, rated 95 °C and 85 °C there (Eq. 14; Figure 8). On cost, S64's $8.52 per GB sold is 2.5% above the 96 GB part's $8.31 and below the 192 GB part's $9.45; 46 and 68 data tiers sit on the cost plateau ($7.51 and $7.50 per net GB), 136 does not ($8.55). Under the tier-yield stresses S64 is cheapest: $11.40 per GB sold at 0.99 per tier against $13.00 and $24.40, $17.80 at 0.98 against $25.60 and $98.80; if the tier adder doubles it ties the 96 GB part at $15.60 ($18.40 for 192 GB) (Eq. 19). It also has the most bandwidth per GB (against the candidates' 42.7 and 21.3 GB/s per GB), the least refresh heat at 105 °C (against 9.43 and 18.9 W) and the highest die yield (against 71.5% and 58.1%). Rated at a 10 ns row cycle, the 96 GB part would win on cost by 2.5% but lose at 0.99 and 0.98 per tier.

Why 64 GB takes 48 tiers. HBM densities are binary, so a 64 GB part must hold 64 GiB, 2³⁹ bits (68.72×10⁹ bytes), of user data. The 46 data tiers hold 69.75×10⁹ bytes (65.0 GiB) after on-die ECC and spare columns; 43 would hold 60.7 GiB, 5% short (Eq. 13). Those three tiers cost 1.05 µm of stack, 0.7 points of yield and $32 per die, and cut the margin at 105 °C and 20 ns from 1.33–1.35× to 1.11–1.13×. Dropping the in-array ECC would let 43 data tiers hold 64 GiB, but the all-MoS₂ cell's retention spread is unmeasured (§24), so we keep it.

If the site is larger. A published HBM5 outline larger than 126 mm² would change the tier count, not the choice:

Cost per GB moves by 1% or less; a larger outline buys rating margin, not cost. An 80 GB part fails the first test on all three, rated 95 °C at 20 ns; it first keeps 105 °C at 20 ns on 145.7 mm² (51 tiers, 49 data + 2 spare; 74.3% yield; $8.40 per GB sold; margin 1.03×), where our rule would pick it over 64 GB at $8.71. We would revisit the capacity only if a published HBM5 outline reached about 146 mm².

Ratings move with the row cycle. The margin assumes reads only at full array access efficiency: host writes (the cell's write pulse is unmeasured), pseudo-channel conflicts and command overhead eat into it; below about 90% efficiency, or past a 20.5 ns row cycle, 105 °C at 20 ns is gone. Duty charges one row cycle per refresh, a read and its write-back on one global bitline; if the write-back needs its own row cycle, duty doubles (the refresh-twice-as-often sensitivity, §3) and S64 is a 95 °C part at 20 ns. At 40 ns the array keeps only 2.60 TB/s of stored bits at 95 °C, so S64 is rated 85 °C there. With listed 28 nm PHY IP it is rated 105 / 105 / 95 °C at 10 / 20 / 40 ns, with 2.08× margin at 105 °C and 20 ns.

Thermal. Side's stack has no bonded interfaces; its vertical thermal resistance is stack height over conductivity and area, with measured back-end layers from 28 nm to 3 nm at about 1–2 W/m·K [59], the dielectric-only case in all three formats (Eq. 17; stack rise in the table above).

Where it fits. With less bandwidth per GB than HBM5 on any reading of Samsung's statements (S64 table; Figure 6), Side suits work bound by capacity: key-value caches, mixture-of-experts weights, long context, large batches and multi-model serving, not bandwidth-bound dense decode. Per GPU die (S64 table; Eq. 21), each 4,096-bit site needs twice an HBM4 site's PHY shoreline, so four sites need twice the shoreline of Rubin's four HBM4 stacks, and HBM5 GPUs' site counts are unpublished.

Cost. Side's yield and cost follow §7–8 at 126 mm² (Eq. 19). Taller stacks do not make bits cheaper; they put more of them in one site. Sweeping die area and tier count, with net user GB and the $85 fixed cost, gives a minimum of $7.45 per user GB at 100 mm² and 64 tiers (Figure 8B, Eq. 20); the cheapest tier count at every area from 50 to 225 mm², and the cheapest area at every tier count from 28 to 120, come within 7% of it, and on the 126 mm² die 30 to 105 data tiers do. The worst corner, 50 mm² with 28 tiers, costs 1.40× the minimum: below the plateau the fixed cost per die dominates, above it compounding tier yield does. Even with perfect tier yield and no fixed cost, the $7.19 tier adder per die-tier alone comes to about $5.40 per user GB, the floor. Tier isolation is unproven; the headline cost takes no credit for it (S64 table).

#Side against HBM5

Bond and Grown are compared with shipping HBM4 in §23; Side is sized for the next generation.

#12Bond in one picture

Van der Waals Bond is six memory tiles under each GPU compute die (Figure 9). Each tile is a tested Van der Waals die on Side's outline and wafer map, its tiers facing up on a silicon base (§13). The six sit two by three under the GPU, with 0.1 mm gaps between them and a narrow band around them, both filled with dielectric. The GPU sits on them face down: its transistors and wiring meet each tile's tiers at a face-to-face hybrid bond of copper pads in silicon carbonitride (Cu/SiCN), and its silicon back faces the TIM, lid and cold plate. Copper vias inside the tiles carry all of the GPU's supply current and I/O down to bumps on a CoWoS-L-class interposer or bridged substrate; no via crosses the gaps or the band. The GPU does all the computing (§17). Nothing bonded has been built.

The host we assume. A reticle-class compute die of 25 × 32 mm (800 mm²) at 1,000–1,250 W, two per package, front-side powered; no GPU maker has published such values for a 2028-generation part (Which GPUs, above; Appendix C). The six tiles cover 756 mm², 94.5% of its face; the gaps take 8.0 mm² and the band 36.0 mm². Every tile reaches the die's edge, so the GPU's edge PHYs route inward onto the edge tiles' vias (§14).

Why tiles. A memory die with the GPU's outline would yield 41% at the design basis's defect density against 76.4% for a 126 mm² tile, and the same 352 GB costs 45% less; six tiles are the cheapest count (§16).

The heat path and the power path. The GPU's own heat path is unchanged; the memory's heat leaves through the GPU, and the tiles run a few K hotter than the GPU above them (§15). The power path runs the other way, up through PhantaField's tiles: about 1.4–1.8 kA per polarity and every off-package signal (§14). That is Bond's main risk. Memory on top of the GPU, as tiles or one die, was rejected: it puts the memory in the GPU's heat path.

#13The bond face and the tile's base

The base. Each tile's silicon base (28 nm in the cost basis; a finer node is a cost decision, not a tier redesign) holds an 8:1 global sense array of 5.73 million sense paths (34.39 M per GPU die), 18.6 µm² of base per path (why 8:1: §3); 128 channel ports; a refresh engine fed by the tile's own thermal sensors; SECDED (72,64) with scrub on refresh; e-fuse and soft repair with tier remap; regulators for the 0.6 V array rail and the wordline boost; guard rings, deep n-wells and dense substrate ties around the sense array where the vias pass; and MBIST and IEEE 1838 test hooks. There is no HBM PHY. Whether all of this fits beside 84,822 vias and their keep-outs in 126 mm² is unverified.

Capacity. 15.3% of each tile is reserved for its vias, their keep-outs and its seal ring (15.29% exact, Eq. 22), its supply field sized for a corner tile, band share included (§14). That leaves 106.7 mm² of array per tile and 640.4 mm² per GPU die, so each data tier holds 8.805 GB raw across the six tiles and 7.706 GB after SECDED and spare columns. Forty-six data tiers give 354.5 GB user-capable, sold as 352 GB (58.7 GB per tile), with two spare tiers on top: 48 tiers, 16.8 µm (Eq. 22). The reserve has 0.60 points of headroom (to 15.89%; §14). Splitting costs array: one die with the GPU's outline would keep 696 mm² and 385.3 GB at 46 data tiers.

The memory port. 768 channels of 640 lanes at 1 GT/s, a 500 MHz DDR clock the base can hold at the 28 nm cost basis, and near the roughly 0.8 Gb/s per lane that d-Matrix's reported 100 TB/s per card implies over its single-cycle links [21]: 491,520 lanes, a bandwidth of 61.4 TB/s per GPU die through 105 °C at a 20 ns row cycle (port limit; §15), 80 GB/s per channel (Eq. 23); 2 GT/s, half the UCIe-3D maximum [63], is the option on a 12 nm-class base (§15). Each tile carries 128 of the channels, 81,920 lanes and 10.2 TB/s. Each channel owns 0.834 mm² of footprint through every tier, 462 MB, and its controller in the GPU sits directly above it. Data goes down a global bitline to a sense amplifier in the base and back up a data tower of spare inter-tier vias, so no through-stack via sits in the data path. NVIDIA has not said it exposes UCIe-3D.

The bond face. A 6 µm Cu/SiCN face on each tile, TSMC SoIC's current pitch (2026), down from 9 µm [64], carries the memory port, the GPU's supply and the signals above that tile, and the rest of its sites are dummy pads. The port takes about 3.6% of a tile's 3.5 million bond sites, shields included. The pad plan also works at 9 µm and at the 4.5 µm TSMC targets for 2029 [64]. No GPU maker has published a pad map.

The bond surface. SiCN dielectric with copper damascene pads, polished to copper roughness below 1 nm and oxide roughness below 0.4–0.5 nm, with the copper recessed 5–10 nm and never protruding [65]. Under it, a landing metal over the last tier ties the supply vias together by polarity and carries them and the data towers onto the bond pads; it adds a few µm and a lateral drop we have not modeled. The surface is the top of a grown stack on a tile thinned for placement; its flatness, copper recess and bow are unmeasured, and no data exists on MoS₂ transistor drift through the bond anneal and the steps after it (§24).

#14Power and I/O through the memory

A GPU bonded on the tiles has no bumps of its own; its supply current and off-package signals come up through vias inside the tiles (concept level):

CoWoS-L-class interposer or bridged substrate → bumps and backside wiring under the tiles → vias through each tile's thinned base and tiers → landing metal and hybrid bond → the GPU's front-side power grid and I/O cells.

The vias are passive copper: no switch or regulator sits in the GPU's path. Their feeds are much coarser than the micro-bumps a CoWoS-class GPU's power grid is designed for (IR drop, below).

• Current. 1,000–1,250 W at 0.70 V is 1,429–1,786 A per polarity per GPU die (Eq. 25). Each tile carries the current over its own 126 mm², a sixth of that over the gaps and, along the die's edges, its share of the band's 80 A by edge length: 239–299 A per polarity in a corner tile, 236–295 A in a middle-row tile. Nothing goes down the gaps or the band; every tile's supply field is sized for a corner. The current over a gap or the band moves sideways in the GPU's grid to the nearest vias, per polarity in one 2 µm copper layer about 0.96 mV at the middle of a gap strip, 5.76 mV at the die's long edges, 0.675 mm from the first vias, and 1.78 mV at its short edges, less with more copper. We give the edges the die's average current; a GPU's edge is mostly PHYs, which draw less. A GPU has several rails (core, SRAM, I/O, PLL, SerDes analog) with their own pads and noise isolation; this model carries one pair.
• Vias. A 5 µm copper via carries 19.6 mA at 10⁵ A/cm², the electromigration rule we assume at 105 °C, the low end of a tested 10⁵–10⁶ range. We run them at half that: 30,453 per polarity in each tile for the GPU's supply. Each tile also carries 8,334 signal and shield vias, a sixth of the GPU's I/O budget, 6,791 per polarity for its own rails and 2,000 for test, 84,822 in all (the 15.3% reserve, §13). Per GPU die that is 508,932, all inside the tiles. Vias through the band's fill instead, 2,048 of 10 µm per polarity, would hold B352 at 46 data tiers and $10.82 per GB sold; we rejected them to keep every via inside a tile (§16).
• Electromigration. At 1,786 A the current density in a corner tile's vias is 5.0×10⁴ A/cm², a 2.0× margin at 105 °C (2.5× at 1,429 A). Black's law with 0.9 eV gives 1.67× at 110 °C and 1.40× at 115 °C. Under 2× local current crowding the margin is about 1×. One via pattern for all six positions (§16) cannot follow the GPU's local maxima: a tile under the SM arrays that carries 1.3 or 1.5 times a corner tile's current keeps 1.54× or 1.33× at 105 °C and 1.08× or 0.93× at 115 °C. Sizing every tile for that costs a 47th or 48th data tier. The foundry's rule at 105 °C will set the real count, within a factor of 10 either way.
• IR drop. 2.95×10⁻⁶ Ω per polarity through one tile's vias and pads: 1.76 mV round trip at 299 A, 0.25% of 0.70 V. Every amp takes this path, so the GPU sees one vertical drop across its face. The I²R inside the tiles is 2.0–3.1 W. Holding the GPU's clocks through the drop costs it 5.0–6.3 W, +0.24–0.29 K at its junction. Spreading in the base, the landing metal and the GPU's top metal is not modeled beyond the gap strips and the edges.
• Package side. At 300–350 mA per C4 bump the GPU needs 5,102–5,952 bumps per polarity, now on the backside wiring across the tiles and the fill, and each tile's own rails get 190–222 per polarity. With about 30,000 I/O bumps (20,000 signals plus grounds) that is about 44,600 bumps, against about 35,556 C4 sites at an assumed 150 µm pitch on 800 mm², so the I/O needs micro-bumps at 40–55 µm, as on CoWoS-L, or bridges under the I/O (Eq. 26). ESD and CDM paths cross a tile before they reach the GPU's clamps.
• I/O. NVLink or co-packaged-optics SerDes, PCIe, die-to-die links (two sets of tiles and the interposer in a two-die package) and any far-tier HBM PHY (about 2,300 signals per stack) all go down signal vias in the tiles. The GPU puts no bond pads over the gaps or the band, and no more I/O over a tile than its allowance: 8,334 signal and shield vias spread evenly, about 66 per mm² and 26 of them signals, so a far-tier HBM PHY would spread over about 87 mm² of tile, far more than its own bump field. The PHYs at the die's edge route inward in the GPU's top metal, past the 0.45 mm band and the seal ring, onto the edge tiles' vias. If they need twice the allowance, the one tile design takes 16,668 (about 132 per mm²), the reserve rises to 16.2% and B352 takes 47 data tiers at $10.80 per GB sold. A via through a tile adds 32–59 fF in 50 µm of silicon alone, plus its run through the tiers and base wiring. High-speed lanes run on one via each in ground-shielded groups with spare lanes and lane repair; only low-speed and sideband signals are doubled: with 20,000 single paths at a 10⁻⁶ open rate, all are good 98.0% of the time. The 20,000-signal budget is unverified; signal integrity is unanalysed and needs joint sign-off with the GPU maker.
• The memory's own power. Up to 50 W per tile, 67 A at 0.75 V (rails sized for 300 W per GPU die), comes up the tile's own package bumps and vias made from the back onto its base's first metal, and feeds the base's regulators (§13). These rails never cross the bond, and each tile's can be switched off at the package (§16). The regulators' loss is counted in the memory's heat (§15), whose full-port rows, at most 246 W, fit within the rails.
• Noise and faults. The GPU's supply vias cross the base silicon that holds the sense amplifiers, with about 1.8 nF of liner capacitance to each tile's substrate, so a 10 mV GPU load step pushes about 18 pC under the sense amplifiers; the coupling into sensing is not yet analysed. The face-to-face bond also puts our 1 GT/s ports and supply pads a few µm from the GPU's top metal over every tile, so the GPU's signal routes there need shielding. The supply vias are massively parallel, so an open is harmless and a supply-to-ground short is fatal to the GPU (leak screen before bonding, continuity after: §16). A short on a tile's own rail switches that tile off; a short from that rail to the GPU's supply keeps feeding it and is fatal.

#15Bond's heat, bandwidth and energy

The GPU's heat path is unchanged. The GPU's silicon faces the TIM, lid and cold plate, so no memory lies in its own heat path; the fill in the gaps and the band sits under the GPU. AMD's second-generation V-Cache made the same trade, its SRAM die under the cores, and claims up to 46% lower core thermal resistance [62].

The memory's own heat goes through the GPU. With the cold side at the Sophon rule of 37.5 mm²·K/W [1], the GPU junction pays P_mem × 37.5 / 800 mm² = 0.047 K per watt of memory power (Eq. 27):

At 61.4 TB/s on the target link the 88 W is 24.6 W of link, 16.8 W of array read and vertical paths, 32.4 W of refresh, 2.0 W of pass-through I²R and 12.3 W of regulator loss. The base datapath and leakage are bracketed, not modeled. A 150 W budget holds 61.4 TB/s on the target link before the base datapath and leakage, and 61.4 down to 18 TB/s with them across both brackets; on a d-Matrix-class 0.37 pJ link, 32 TB/s without them and 24 down to 6 TB/s with them.

The memory runs hotter than the GPU. Each tile sits at the local GPU junction plus the rise that pushes its own heat up through its tiers, its base back end, the bond layer and the GPU's back end: 13.0–32.8 mm²·K/W over the 756 mm² the tiles cover (Eq. 28). That is +1.5–3.8 K at 61.4 TB/s on the target link, +2.1–9.4 K with datapath and leakage, and +2.6–6.5 K at the 150 W budget. For a 105 °C memory rating the GPU junction over the tiles stays at or below about 98 °C at a 150 W memory budget, and 94–101 °C at 61.4 TB/s, by link (the §16 table). The cap binds the GPU's hot spots almost everywhere, since the tiles cover 94.5% of its face. Against a native hot-spot limit of 105–110 °C, the 98 °C cap plus the memory's own heat costs the GPU 14–19 K of headroom, up to about 289–396 W of its power at 0.047 K per watt, an upper bound that treats the flux as uniform (Figure 11). At 110 °C refresh would take 53.3% of the sense paths at a 20 ns row cycle, over the 50% rule, though the tiles would still deliver 61.4 TB/s (port limit).

Refresh, hot next to cool. 0.16 / 8.10 / 16.2 / 32.4 W (about 0.46 / 23 / 46 / 92 mW per GB sold) at 25 / 85 / 95 / 105 °C; a 25 °C these tiles never see under load. HBM self-refresh is 23–52 mW per GB (temperature not stated). At 85 °C refresh costs what HBM's self-refresh does; at 105 °C about twice HBM's top figure (§3). The rating follows from the refresh duty (§3; §16 table).

A second heat path. We ignore the path down into the substrate and the cooler gaps, conservative for the memory. Package-side or double-sided cooling, worth about 17 K in imec's HBM-on-GPU study [27], would cool the memory directly and is the best lever if the GPU maker offers one.

Bandwidth: 61.4 TB/s through 105 °C at a 20 ns row cycle (port limit). Per GPU die that is 5.6× a Rubin die's 11 TB/s. Behind the port, the sense array can move 34.39 M paths ÷ row cycle ÷ 8: 430 / 215 / 107 TB/s at a 10 / 20 / 40 ns row cycle before refresh, less the share refresh takes (Eq. 23):

At 20 ns the port takes 32 / 35 / 46% of the slots refresh leaves free at 85 / 95 / 105 °C (bank conflicts are not modeled). At 10 ns the port is the limit, with 287 TB/s of array to spare at 105 °C. Bandwidth per GB is 175 GB/s per GB at 95 °C and a 20 ns row cycle, against 57–92 for HBM4, and the whole 352 GB can be read in 5.7 ms, against 13.1 ms for a Rubin die's 144 GB. Moving 61.4 TB/s across the die costs up to 43 W per mm of mean travel (a CV² bound, Eq. 44), and the GPU must keep 58,000–96,000 64-byte requests in flight at 60–100 ns of loaded latency. On a 12 nm-class base [56] whose back end meets the tier budget (§6), at 2 GT/s per lane, half the UCIe-3D maximum, Bond would carry 122.9 TB/s per GPU die through 95 °C at a 20 ns row cycle (port limit; 11× a Rubin die's 11 TB/s), at 105 °C only at 92% slot efficiency, with +6.3–14.6 K at the GPU junction at that bandwidth. At 0.8 Gb/s per lane, the rate d-Matrix's early silicon implies, it would carry 49.2 TB/s per GPU die through 105 °C at a 20 ns row cycle (port limit; 4.5×).

Energy: a bracket. Moving a bit from the cell to the GPU's receiver costs 0.08–0.4 pJ (Eq. 24): about 0.03 pJ in the array read and the vertical wires, plus a bond link of 0.05 pJ at the low end, the UCIe-3D target [63], or 0.37 pJ at the high end, d-Matrix's company-reported vertical link on early silicon at a 36 µm face-to-face pitch, which includes its datapath (its ISCA 2026 paper gives 0.455 pJ per bit at full switching and 0.376 with stream flipping) [21]. The base's datapath (SECDED, the global-bitline multiplexer, latches and lane drivers) and the GPU's on-die network are not included. Against HBM4's 2.4–4 pJ (secondary sources [20][21]) that is 6 to 48 times less; with an assumed 0.03–0.10 pJ datapath it is 0.11–0.50 pJ, 5 to 35 times less. At Rubin's 22 TB/s, HBM4 traffic costs 422–704 W against B352's 28–86 W (table above).

#16Bond's yield, cost and configuration

Six tested tiles. Each tile yields like the 126 mm² die it is: 88.3% die yield at 1.26 cm² and D₀ = 0.1/cm² (§8), times 0.997⁴⁸ for its tiers (§7), is 76.4% tile yield, 87.6% with tier isolation (Eq. 29); a defect in the 5.5% of each tier that the vias and towers occupy is fatal to the tile, and the leak screen before bonding catches it (Test, below). A 300 mm wafer holds 501 gross tiles: 383 good, 63 GPU sets (439 and 73 with isolation).

How a stack is made, by function. The flow is shared with a host under a non-disclosure agreement. The tiles are made on PhantaField's wafers: a silicon base (28 nm in the cost basis; a finer node is a cost decision, not a tier redesign), tiers at 28 nm design rules, the GPU's supply and I/O vias through the tiers into the base, and the bond layer, so the vias are leak-tested with the memory before bonding (Test, below). The sorted GPU wafer gets a bond layer instead of bumps and is the bond target and permanent carrier, so the backside steps need no temporary carrier. Tested tiles go face down onto sort-good GPU sites, six per site, with dummy silicon on failed and partial sites: about 320 placements per GPU wafer, 10–12 minutes at 1,600–2,000 placements an hour [64]. Then fill and planarize; thin the tiles from the back to open their vias; add each tile's rail vias from the back; backside wiring and bumps; wafer-level test; singulate and flip onto the interposer or bridged substrate. No via crosses the fill, so the flow has no deep oxide etch through it (about 77 µm and 1.3–4.3 hours per wafer for the band vias rejected in §14), no liner or copper there, and no via beside a seam where the fill closes. A sort-tested GPU is not burned in (Test, below).

The alternatives. A reconstituted tile wafer as the bond target would put every GPU across six tiles and their fill, a 756 mm² face that must meet hybrid-bond flatness across tile edges, with no production precedent, and would handle each tile twice; bonding the GPU onto tiles already fixed to a base meets the same flatness problem. Collective bonding, six tiles held on a carrier and bonded to the GPU wafer in one step, saves placement time and particle exposure at the cost of about 1 µm of die shift, tight at a 6 µm pitch. Whole-wafer bonding cannot place six tiles per GPU site and gives up tested-tile selection.

Into the package. The GPU maker's CoWoS-L-class interposer, or a substrate with embedded bridges under the I/O (§14), with TIM, lid and cold plate on the GPU's back. Each tile ends about 77 µm thick; with the GPU's silicon thinned to about 675 µm under its 10–15 µm of front wiring, the stack stays within 775 µm. Package reflow comes after the stack's final test and hot retention screen, so MoS₂ drift through it must be measured too (§24).

Mechanics. A tile is placed with about 100 µm of silicon under 25 µm of tiers and base wiring, about 130 µm tall on the GPU wafer, and by Stoney sags about 26 µm per 10 MPa of net film stress across its diagonal; the bond pulls a small bow flat, but a tile concave toward the bond face traps voids at its centre, so the tiles are specified convex by at most about 10 µm with no edge lift, which holds the net stack stress to about 3.8 MPa with a balancing film on the tile's back, or places them thicker at the cost of a deeper fill. The fill must reach the tiles' 130 µm before both are ground back; as one blanket film at 20–100 MPa it would bow the 300 mm GPU wafer by about 1.6–8.1 mm before polishing, and no published oxide gap fill is that deep, so it must be low-stress (Eq. 29). Singulation then cuts about 77 µm of brittle fill and the GPU's silicon within 0.15 mm of a bonded tile's edge, where chipping or delamination can reach the bond.

What a failed stack costs. Splitting does not raise bond yield; it adds placements. On the basis we used for one GPU-size die (a bond yield of 0.80–0.98 for 800 mm², voids scaling by area) each 126 mm² placement yields 0.966–0.997 and six together 0.81–0.98; published die-to-wafer yields of 98% at 70–100 mm², scaled to one tile, give 0.964–0.975 per placement. For the losses that come once per placement (edge and dicing particles, placement error; six tiles have 270 mm of edge against 114 mm for one die) we add 0.99–0.995 per placement and 0.975 for the bonded-wafer steps. A liner short from any of the GPU's 182,718 supply vias to a tile's substrate also loses the stack: the chance of none is 0.998, 0.982 and 0.833 at 10⁻⁸, 10⁻⁷ and 10⁻⁶ per via, rates for damage done after the leak screen (Test, below). A failed tile bond scraps the GPU unless it opens only memory-port pads. SK hynix sets a 90–98% yield bar before it will adopt hybrid bonding in memory [68].

Counting a scrapped GPU at $5k to $20k, that is $13.03–35.56 per GB sold per good stack (the single die: Cost, below). Per-placement losses favour fewer tiles: at 0.995–0.99 per placement, in 6 of 8 cases, four tiles beat six ($18.26 against $19.44 at a bond yield of 0.98, a $20k GPU and 0.99 per placement).

Cost. The tile wafer costs $3,500 for the base (priced at 28 nm), 48 × $3,600 for the tiers, and two tier-equivalents for the through-stack vias and the bond layer with its landing metal: $183,500, or $564 per tile over 501 gross tiles at 76.4% with $85 of test ($503 with tier isolation). The GPU wafer carries five more tier-equivalents (§8): $352 per sort-good GPU at a sort yield of 0.8. All seven adders are unsourced. A set of six tiles is $10.62 per GB sold ($9.58 with tier isolation) (Eq. 29). The rejected alternative, one memory die with the GPU's outline, would yield 41.0% and cost $19.14 per GB sold ($16.73 with tier isolation), or $41.35 at an area-scaled 0.981 per tier for 800 mm², so the tiles are 45% cheaper, or 74% against the area-scaled figure. Per good stack that die costs $21.57–42.23 against the tiles' $13.03–35.56 on the matched basis, and $20.53–38.95 against $11.56–27.98 on its own area-only basis. B352 costs 1.6× the crude HBM cost proxy of $6.57 (§8) and 1.25× Side's S64, and less than the 2H26 HBM4 contract price of about $16 per GB [48]. Left out (§8): a hot retention re-screen after bonding would add $0.24–1.45 per GB. Sensitivities: $11.62 per GB with the GPU-wafer adders doubled and $14.61 at five times; $13.26 with every adder tripled; $11.22 at a GPU sort yield of 0.5; $10.13 at D₀ = 0.05/cm²; $9.40 with test scaled to tile area.

Per-tier yield. Without isolation B352 costs $13.90 per GB at 0.99 per tier and $17.06 at 0.985; with isolation, $9.79 and $10.04. If tier defect density scales with mask count, a 126 mm² tier yields 0.989–0.993 (Eq. 38) and B352 costs $14.55 ($9.84 with isolation).

The configuration.

Why B352 in six tiles. Bond is chosen by the sequence of §11 on its own rating criterion (§3), inside two family limits: Bond must hold less than Grown's 416 GB (C1), and Grown must deliver more than Bond at every matched memory temperature and row cycle (C2, §20). The candidates are four, six, eight and twelve tiles in the same envelope, at every size from 128 to 512 GB on a 32 GB grid, with the fewest data tiers that cover it; Bond keeps 48 tiers per tile, as Side does and as Grown does below tier P. One tile design serves all six positions, its uniform via pattern sized for a corner tile's current and a sixth of the GPU's I/O; each GPU program needs its own tile design. Only B352 in six tiles is offered (Eq. 29):

At 48 tiers (C2 needs at least 46 data tiers) four and six tiles hold B352, eight and twelve only B320. Six tiles are cheapest, since fewer, larger tiles lose die yield (0.830 at 190 mm² against 0.883), more and smaller ones each pay $85 of test, a seal ring and two spare tiers, add gap, and their reserve rises to 16.1% at eight and 17.2% at twelve. Four are 2.9% dearer (2.2% with isolation), outside §11's 2% tie, on a 12.0 × 15.8 mm tile that shares no outline or wafer map with Side; six reuse Side S64's outline, 501-site wafer map and tier process (its own masks: §4). With the tiers left free the rule would pick B384 in six tiles at 50 + 2 tiers ($10.42, 1.9% cheaper), and without the two family limits as well B416 ($10.26), so the 48 tiers and the limits cost Bond 3.4%. Every size up to B448 passes the rating; B480 and B512 take more than half the sense paths at 105 °C and 20 ns and need more than 64 tiers (§19).

What would move the choice. At 48 tiers no stress we ran moves it: 0.99 or 0.985 per tier, tier isolation, mask-scaled tier yield, test scaled to tile area, adders tripled, a GPU sort yield of 0.5 and D₀ = 0.05/cm² all leave B352 in six tiles. Per good stack with per-placement losses, four tiles win in 6 of 8 cases (What a failed stack costs, above).

Redundancy and tile map-out. Spare columns (4 per 256), two spare tiers per tile with remap, SECDED with scrub, spare lanes with repair after bonding, and channel map-out. Tiles add one more level (concept level): a tile whose memory fails after bonding, from a test escape, a retention shift or a short on its own rail, can have its rails switched off at the package and its 128 channels dropped from the GPU's address interleave, while its passive vias keep serving the GPU above it. That needs the GPU to disable the dead tile's 81,920 lane drivers, fail-safe I/O on both sides and six switchable memory rails per GPU die, none of it costed. Whether such parts are sold is not decided; the cost here assumes every good stack sells at 352 GB. Still fatal: a bond failure that opens a tile's supply field, the supply shorts of §14 and GPU sort escapes. A bonded tile cannot be replaced.

Test. Before bonding, each tile gets MBIST, retention at 85 and 105 °C, column and tier repair with remap, a supply-to-ground leakage test, and a leakage test of every through-stack via against the substrate and, with the memory nets biased, against the tiers' and base's own wiring, the liner screen; shorts made later, as the bonded tile is thinned and its vias revealed, are found only after bonding, as is via continuity, and the rail vias do not exist yet. After that test the tile still sees the bond layer, thinning, dicing, the bond anneal, the reveal and the backside steps, so retention shift, MoS₂ drift and thin-die cracks can escape it. After bonding, at wafer level through the new bumps: GPU test, via continuity, tile MBIST over IEEE 1838 across the bond, tier and channel remap, a hot retention re-screen and lane repair. No probe or wafer test pushes 1.8 kA, so a partial open in a tile's supply field is invisible until package test or the field.

The first vehicle (proposed). One 126 mm² tile with a few tiers, bonded under a dummy logic die that draws a programmable 299–600 A through its vias, beside filled gaps and a filled band with no via in either, their current fed sideways into the tile. It would measure the through-stack via etch and liner and the leak screen before bonding, tile bow, fill depth and wafer bow, the reveal and the backside vias, singulation through the fill, electromigration at 105–115 °C, IR drop, die-to-wafer yield per placement on a grown-stack surface at 126 mm², a collective-bonding split, and MoS₂ drift through the bond anneal and the backside steps.

#What the GPU maker builds

• An interface agreement. No GPU maker has published a bond interface, pad map, die outline or power for a 2028-class compute die (Which GPUs; Appendix C).
• A front-side-powered compute die, bonded face down onto the tiles (Which GPUs; Risk 33).
• Its wafer as the bond target and carrier: sort, then a hybrid-bond layer with six tile footprints instead of bumps and no bond pads over the gaps or the band (How a stack is made, above; §14).
• A line that places six tiles per GPU, fills, thins, reveals the vias and builds the backside, and qualifies third-party tiles that contain MoS₂ and sulfur [64] (How a stack is made; Mechanics, above).
• A power network fed only through our tiles, with every rail's pad map registered to one via pattern and top metal that carries the band's 80 A per polarity to the edge tiles (§14).
• All off-package I/O through our tiles, within each tile's I/O allowance, with joint signal-integrity and ESD sign-off (§14).
• 768 memory channel controllers that honour each tile's refresh windows and can map a tile out (§15; Redundancy, above).
• A GPU junction cap and a memory power budget (§15).
• Test access through the bond and an ECC policy (Test, above).
• A tile design per GPU program, and terms: a film-stress budget for the tiles and the fill, and who pays for GPUs scrapped by failed bonds, placement losses or a short in a tile's power path (Mechanics; What a failed stack costs, above).

#17Grown in one picture

Van der Waals Grown is a back-end process module, not a die: the GPU maker's foundry finishes the GPU wafer through its last thick metal, NanoGalaxy tools grow the memory tiers and then tier P, the periphery tier, in a dedicated module area, and only pads, bumps, assembly and burn-in follow (§19). Nothing has been grown on a GPU, or on any logic wafer, yet.

The lead host. A front-side-powered, flip-chip compute die of the N3 or N2 class; TSMC's first node with backside power is A16 [42]. A flip-chip die's front, with its wiring and bumps, faces the package and its silicon the cold plate, so tiers grown between the last metal and the bumps stay out of the GPU's main heat path (Figure 10).

The configuration. On an assumed 800 mm² die the array covers 768 mm² after a 4% tower field, so each data tier holds 9.24 user GB, 19.9% more than a Bond data tier's 7.71 (Eq. 30, §20). G416 is the one Grown part, chosen to hold more than Bond and to deliver more than Bond at the same memory temperature, row cycle and cell retention, with lanes above 119 MHz (§20):

Not Sophon. Grown puts memory on someone else's GPU, and the GPU does all the computing. Sophon, PhantaField's own compute-in-memory chip, is a published 750 mm² design of 64 tiers on its own silicon base, logic tiers and memory tiers alternating [1], and its 64 tiers are a design target (§19). Grown borrows Sophon's cell and tier, not its architecture.

#18Tier P and the periphery partition

With no base die, the sense amplifiers live on a periphery tier of our own, tier P, grown in the same module; every memory tier stays identical to Side's and Bond's. Tier P holds the 8:1 global sense array, 41.24 M sense paths per die (53,696 per mm² over 768 mm², Eq. 31), and hands the data down to the GPU's top metal on 4.12 M short vertical lanes, about 5,370 per mm², at a 500 MHz design rate, unmeasured, so the GPU gives up no transistors to sensing. The integration flow, the lane plan and the tower layout are shared with a host under a non-disclosure agreement.

• Tiers (48, two of them spare). The family's nFET-only tier, one growth pass each, with an 8:1 column multiplexer; every cell is all-MoS₂, since no tier can reach the GPU's silicon transistors under its back end for a read transistor. 4% of every tier is the tower field.
• Tier P. Its transistors are 2D: nMOS-only MoS₂, or MoS₂ with WSe₂ if the sense latch must be complementary. Neither has been measured as a sense latch, and p-type 2D transistors have not reached the switching slope the design assumes.
• Why 8:1. At 16:1, G416's refresh duty at 105 °C and a 20 ns row cycle would be 75.4%, so the part could not be rated at GPU temperature (§3).
• What the GPU builds. Lane receivers and landings for the 4.12 M lanes, which take about 0.5–2.1% of its top-metal landing sites at a 1–2 µm pitch and pierce its top power mesh (Eq. 40); about 768 channel controllers, one per mm² of array, each serving 0.554 GB at up to 336 GB/s, with queues, row and refresh scheduling and credits; a refresh engine fed by the GPU's own regional thermal sensors; SECDED with scrub on refresh; repair and remap tables; MBIST, channel map-out, RAS logging and the address interleave. Their area is not estimated; they are simpler than today's memory controllers (no PHY, no DRAM protocol), which Samsung puts at 5–10% of an XPU [25], but come on top of what the GPU already carries.
• Rails. The memory's own supply arrives separately from the GPU's and can be cut off, so a short on a memory rail becomes a memory fault, not a dead GPU (concept level).
• Not needed. No PhantaField base die, no PHY, no bond lanes, no TSVs, and no ESD on memory lanes, which are internal wires.

The fallback: sense amplifiers in the GPU (option A). If the tier-P latch fails its gate, the GPU can host the sense array in its own transistors: proven devices and one tier fewer, but at an assumed 1–2 µm² per sense path it costs 41–82 mm², 5.2–10.3% of the die, and 53,696 bitlines per mm² must descend through every signal layer, taking 5.4–21.5% of the top-metal landing sites over the array at a 1–2 µm pitch (Eq. 40). On a front-side-powered host they pierce the top power mesh; on a backside-powered host the front top metal carries no power, so option A fits that attachment better (§21). At 1.93× the sites of a 6 µm hybrid bond, option A can exist only monolithically.

The gate. A measured tier-P circuit: a MoS₂ sense latch that resolves a 2T0C bitline at 0.6 V inside the 18.6 µm² each path gets (768 mm² ÷ 41.24 M), with its hand-off to the GPU running at speed (§20), at 85–105 °C, after a full tier thermal history and after bumping. MoS₂'s threshold is strain-sensitive, so bump and underfill stress on latch offset is part of the gate. An nMOS-only output stage also swings only to V_DD − V_t unless boosted, so reaching the GPU's 0.75 V receivers needs level conversion. If the gate fails, the front-side lead falls back to option A, or the lead moves to the backside attachment.

Later (concept only). Tier-local refresh, a latch on every memory tier and not only tier P (§25).

#19Flow, thermal budget, contamination and patterning

Four things decide whether a foundry can run the module (Figure 10): the thermal budget, contamination, the patterning load and the GPU's own back end.

The flow, by function. The foundry finishes the GPU through its last copper metal, with a landing grid from our design kit in the top metal, and prepares the surface for growth; its probe pads do not exist yet, so only scribe-line monitors are read. In the module area each memory tier is grown with one NanoGalaxy MoS₂ pass at the host-qualified temperature, patterned at 28 nm design rules and inspected inline, and tier P, at the same rules, with one or two passes. After the tiers come only the pad and redistribution layer the GPU would have had anyway, bumps at their original x-y positions plus the memory-rail bumps, joint wafer sort with repair written at sort, assembly, and burn-in with a hot-retention screen. Final bins are full capacity, reduced capacity, or no near memory if HBM stays beside the die as the far tier.

Thermal budget. NanoGalaxy's published basis is growth below 450 °C [3], above the convention of about 400 °C for copper/low-k back ends [40], and no foundry publishes a time-at-temperature budget for N3, N2 or A16 [42]. Every tier step must stay at or below the host's qualified limit, and the budget is cumulative over G416's 49–50 growth passes (one per memory tier, one or two for tier P). At about a minute of growth per pass, the growth window alone uses 82–83% of the one hour above 400 °C that the only public anchor allows a finished back end (§6) [44]; the whole chamber time, about four minutes per pass, is 3.3× that hour unless the wafer stays below 400 °C outside the growth window (Eq. 41). Each tier's dielectric depositions and via fill add thermal steps not counted here. Two cases: if growth runs above 400 °C, G416 exceeds the anchor once chamber residence or those steps are counted; if every step stays at or below 400 °C, the anchor does not bound it, and there is no tier data at that temperature. No host has qualified a budget of that length. Neither Bond's 48 tiers on its own silicon bases nor Sophon's 64 design-target tiers stand in for this budget (§6). The thermal-history twin is the first gate (§6, §25).

Contamination. Molybdenum is entering production, by vendor account: Lam's ALTUS Halo molybdenum deposition (February 2025, with Micron named, for 3D NAND) and Applied Materials' Spectral molybdenum contacts for logic (February 2026, at unnamed 'leading logic foundries') [70][71]. Sulfur, chalcogen and metal-organic precursors have no public fab limit [72]. Detection reaches about 10⁹–10¹⁰ atoms/cm² by TXRF and 10⁶–10¹⁰ by VPD-ICP-MS [72]. On the lead host only pad, bump and assembly tools see a wafer with tiers, so a one-way flow on the copper template is natural; it proves nothing until a fab sets limits.

Patterning load. Added mask levels are total tiers × m, where m is masks per tier. IBM's 14 nm embedded MRAM added three masks [45], but it inserts a device between existing metal levels and reuses the host's transistors and wiring: a precedent for module integration, not a floor for a tier. A Van der Waals tier builds its own transistors and wiring (channel, gate, contacts, at least one local metal and the vias): about five levels at minimum, about eight with three local metal levels. At m = 5–8 that is 245–392 added levels for G416, against about 90 layers for a whole 3 nm flow [1]: 2.7–4.4×, all on the GPU's most valuable work in progress (Eq. 41); at 8–10 per tier it is 392–490. Fab time is the host's number: 245–588 days per GPU wafer at 1.0–1.5 days per mask layer, or 122–196 days at half a day per layer as a hot lot. Carried at 10% a year, that is about $7.9k–19.3k per wafer, $0.37–0.91 per GB at a GPU yield of 0.8, before the time to market lost against a GPU generation of one to two years: probably the largest schedule cost of this format.

Stress. A 17.15 µm stack bows a 300 mm wafer about 107 µm for every 10 MPa of net film stress, so the films of all 49 tiers must be balanced to about 10 MPa net or less; at 30–50 MPa the bow would be 320–534 µm, beyond typical chuck and bond limits (Eq. 42). Stack stress, flatness and delamination resistance are unmeasured; microbumps and underfill will sit directly on a 17 µm stack with van der Waals interfaces.

#20Grown's power, heat, bandwidth, yield and cost

#Power and I/O

The GPU's power climbs through the tiers: package, microbumps at the original x-y map, pads rebuilt on the stack, towers through 17.15 µm of tiers, landings on the GPU's top power metal, then its own grid. The towers carry only GPU current; the memory never draws from the GPU's grid.

• Current. 1,333 A per polarity (1,000 W at 0.75 V), up to 1,786 A (1,250 W at 0.70 V), on our assumed host; Bond takes 0.70 V throughout (1,429–1,786 A), and both formats are sized at 1,786 A.
• Metal. At tungsten's electromigration limit of 5×10⁵ A/cm², both rails need 0.53–0.71 mm² of metal; as 45 nm via arrays at 19.6% fill, 2.72–3.64 mm², or 0.34–0.46% of the die (Eq. 35).
• Towers. Sized to the bumps they feed, at an assumed 25 mA up to about 65 mA per micropillar in a GlobalFoundries patent [73], the power and ground towers take 0.53–0.89% of the die at minimum size, 1.7–2.6% oversized 4×, inside the 4% field (Eq. 35).
• IR drop. At the electromigration limit the bulk-resistivity floor is J × ρ × h, independent of current: 17.15 mV round trip, 2.3% of 0.75 V. The floor treats each tower as one continuous tungsten via at 10 µΩ·cm; a lined 45 nm via runs nearer 20–30 µΩ·cm, and each of the 49 tier segments adds a contact comparable to the via body, so the real drop at minimum size could be 2–3× the floor, 4.6–6.9% of the supply, more than a GPU's whole IR budget. The design point is therefore towers oversized 4×: 4.3 mV (0.57%) at the floor, 1.1–1.7% with liner and contact terms, 2.4–7.3× the 1.76 mV Bond's copper vias drop (Eq. 36). Holding the GPU's frequency against that drop costs 11–43 W of dynamic power on a 1,000–1,250 W GPU, +0.5–2.0 K at the junction, or about 1–2% of frequency given up; Bond's 0.25% drop costs it 5–6 W, +0.2–0.3 K (§15). Copper vias made after the last tier, as in Bond's tiles, are a concept-level alternative.
• Tower heat. At the 4× design point, 5.7 W at 1,333 A on the floor, up to 23.0 W at 1,786 A with liner and contact terms: +0.3–1.1 K at the junction. Minimum-size towers would dissipate 22.9–30.6 W on the floor (+1.1–1.4 K), and 2–3× that with liners.

The floors assume current spreads evenly. Crowding at the bumps, di/dt noise coupling into 2T0C storage nodes beside the towers, and the signal integrity of SerDes and HBM-PHY signals through 17 µm towers (about 2.7 fF each) are not yet analysed. ESD stays in the GPU's transistors; the towers only pass through.

The memory's own supply. The memory's rails draw 26 A at 22 TB/s and 85 °C, and 124 A at 95 °C and 135 A at 105 °C at a 20 ns row cycle, upper bounds that charge all access energy to the 0.6 V rail; at 25–65 mA per bump that is about 400–5,400 added bumps per polarity (Eq. 37).

Containment. A dead or shorted lane, tier or memory rail stays a memory fault (concept level, §18). The GPU can be armoured against its memory electrically, not mechanically or thermally: delamination, chip-package interaction under the bumps, thermal damage to its back end, plasma charging of landing nets and contamination are process-level killers that spare tiers do not cover.

#Heat

On the lead host the tiers sit on the bump side, out of the GPU's main heat path, so the 4% field holds towers and no thermal columns. Memory has shipped on the package side of logic before, in AMD's second-generation V-Cache [62] (§15), a bonded die, not a grown stack. The small, unpublished share of GPU heat that leaves through the bumps now also crosses 17.15 µm at 1–2 W/m·K, 9–17 mm²·K/W in series with the package; we have not included it.

The junction pays the memory's own heat, the towers' heat and the GPU power that holds its clocks through the tower drop. With P / 800 mm² × 37.5 mm²·K/W (Eq. 34, 36):

Bond's terms are in §15. At 61.4 TB/s and 105 °C, G416's own heat is +2.6 K, +3.4–5.7 K with the towers and the clock hold (Eq. 36), against about 4.4 K for Bond; at 22 TB/s, G416's +1.5–3.8 K overlaps Bond's +1.6–4.3 K. Grown's is lower at high traffic only if its tower drop stays near the floor (Figure 11).

Memory temperature. The memory runs at the local GPU junction plus its own drop, 0.05–0.6 K at 22 TB/s and 0.25–3.25 K at 105 °C and a 20 ns row cycle, so a 105 °C memory rating keeps the GPU junction under the memory at or below about 102 °C at that point, or about 104 °C at 22 TB/s. Over a 2.5 W/mm² local maximum the memory runs at that spot's temperature, and its refresh rate doubles every 10 °C; the GPU's regional sensors set each channel's refresh rate. G416 refreshes 20% more bits than Bond and draws 20% more refresh power, the same per user-capable GB (§3).

#Bandwidth

Grown's bandwidth is set by its array at 20 and 40 ns and by its lanes below about 14.5 ns. The array moves 41.24 M paths ÷ row cycle ÷ 8, 258 TB/s at a 20 ns row cycle before refresh; tier P's 4.12 M lanes at their 500 MHz design rate, unmeasured, carry the same 258 TB/s, so the lanes bind only if the row cycle is 14.5 ns or less at 105 °C (18.3 ns at 85 °C). Refresh at GPU temperature takes its share of the array (Eq. 32). The table gives the lesser of the two against Bond's at the same memory temperature and row cycle; G416's figures assume lanes at 406 MHz or more, against a 500 MHz design rate, unmeasured, and the 10 ns row the full 500 MHz:

Why Grown moves more. At the same memory temperature and row cycle, for the same cell retention, and with its lanes above 119 MHz, Grown delivers at least 1.1× Bond wherever Bond delivers anything: 3.8 / 3.4 / 2.6× at 85 / 95 / 105 °C and a 20 ns row cycle, 1.7 / 1.3 / 1.2× at 40 ns, from 20% more sense paths, with the same 46 data tiers to refresh. The sense paths are area: a 4% tower field instead of Bond's 15.3% via reserve, and no seal rings or gaps, leave each Grown tier 768 mm² for cells against 640.4 mm² across Bond's six tiles, so 46 data tiers carry 41.24 M sense paths against Bond's 34.39 M, 1.199×, at the same 2,049 bits per path per tier. The second reason is Bond's port, a design choice, not a limit of bonding: it takes about 3.6% of its tiles' bond sites (§13). Bond could widen its port toward the 174 TB/s its array leaves at 95 °C and a 20 ns row cycle (array limit), but every added TB/s crosses the bond as link energy that heats the GPU (Eq. 32). Grown's lanes are on-die wires with no link energy.

The conditions. The claim holds under four conditions.

• Lane rate. Tier P's lanes must run at 119 MHz or more to deliver more than Bond's 61.4 TB/s at row cycles of 10–20 ns, and at 406 MHz or more, against a 500 MHz design rate, unmeasured, for 209 TB/s at 95 °C and a 20 ns row cycle. At 200 MHz they carry 103 TB/s, above Bond's port, and the smallest ratio is still 1.199×, at Bond's array limit. The 500 MHz figure is Sophon's design value for a lane through a TMD stack, unmeasured.
• Retention, row-cycle and access-efficiency parity. Both sides take the same cell retention, row cycle and access efficiency. Over 85–115 °C in 0.5 K steps and row cycles of 10–40 ns, the smallest ratio wherever Bond delivers anything is 1.199×, at 103 °C and 38 ns; it holds on a grid out to 80 ns (at least 1.199×) and is at least 1.199× at any shared access efficiency from 0.7 to 1.0; at 20 ns it is 1.96× at 110 °C (120.3 against 61.4 TB/s, Bond's port limit) and 1.20× at 115 °C. Grown's margin against a refresh or row-cycle penalty of its own is not yet computed against the six-tile Bond. Parity is not given: Grown senses with an unmeasured TMD latch in tier P and grows at the host's limit on the GPU; Bond senses in the silicon base of its own tiles.
• Temperature basis. The comparison is at matched memory temperature. On a matched GPU junction the offsets overlap: Grown's memory sits 0.25–3.25 K above the local junction at 105 °C and a 20 ns row cycle (0.17–2.21 K at 61.4 TB/s), Bond's tiles 1.5–3.8 K above at 61.4 TB/s.
• The GPU side. At a 20 ns row cycle both formats exceed what a GPU takes in today: an H100-class die's SMs can load at most about 33 TB/s from L1 in all (our estimate, Eq. 44), and its L2 and on-die network carry less; at 105 °C and a 40 ns row cycle both fall below it (Bond 26, Grown 32 TB/s). Where the network is the limit both deliver its rate and tie: under a cap at or below Bond's 61.4 TB/s the ratio is 1.000 at every 10 and 20 ns point through 105 °C. At G416's 95 °C, 20 ns figure (table above) and 60–100 ns of latency the GPU must keep 196,000–327,000 64-byte requests in flight, and each mm of mean on-die travel costs up to 146 W (0.087 pJ per bit and mm, a CV² upper bound; about 36 W for random data; Bond: §15), with a global address interleave on a 25 × 32 mm die averaging 19 mm (Eq. 44). The surplus is usable only if data is placed over the processors that read it, and a host will power-cap the memory.

Energy per bit. 0.03 pJ, cell to GPU receiver: the array read plus a vertical wire of at least the stack height plus 5–15 µm of the GPU's back end, at most twice that (Eq. 33). It leaves out the tier-P latch, the GPU's receivers, ECC and the on-die network, so it is not ranked against HBM4's 2.4–4 pJ or Bond's 0.08–0.4 pJ.

#Yield

Grown's tiers are grown on untested GPUs, so memory and GPU yields multiply (Eq. 38). Without tier isolation, 0.997⁴⁹ = 86.3%: G416 would lose 13.7% of otherwise-good GPUs, $71, $793 or $3,172 of scrap per good assembly at illustrative GPU die values of $450, $5k or $20k, and holding that loss to 1% would need 0.99980 per tier, 14.6× fewer killer defects than the 0.997 basis. Isolation is mandatory. With it and two spare tiers, full capacity holds at P(≤2 of 48 fail) = 99.958%, and the GPU is lost only to the share f of tier failures that short a GPU tower or rail: 49 × 0.003 × f, 0.15–0.59% at f = 1–4%; keeping that loss at 1% or below needs f ≤ 6.8% (2.0% if each tier fails 1% of the time). Tier-P defects map out channels and become capacity bins; a tier short onto a GPU tower still kills the GPU.

Towers against the fatal share. The towers that hold the IR drop take 1.7–2.6% of each tier at 4× oversize. If tower area stands in for the GPU-fatal share, GPU loss is 0.25–0.38% at 0.997 per tier, or 0.59% if the whole 4% field counts; at the mask-scaled tier yield below it is 3.6–8.4%, or 8.2–12.6%, 4–13× the 1% target. IR drop and the fatal share trade against each other.

If the 0.997 basis is optimistic. If an 800 mm² tier's killer-defect density scales with its 5–8 patterning levels from the host's own D₀ (0.1/cm² over about 90 levels, about 1.1×10⁻³/cm² per level), each tier yields 0.93–0.96, not 0.997. Without isolation G416 would then keep only 3–11% of otherwise-good GPUs; with it, full 416 GB only 35–65% of the time, so 416 GB could be the minority bin, selling 394–405 GB on average after downbinning on a 32 GB grid, and GPU loss at 1% or below would need a GPU-fatal share of 0.3–0.5%, not 6.8% (Eq. 38). The defect density of an 800 mm² tier is the first thing a Grown vehicle must measure; the 0.997 basis was set at 126 mm² (§7).

Capacity margin. G416 holds 425.1 GB user-capable, 9.1 GB (2.2%) more than it sells, so the tower field can grow from 4% to 6.1% of each tier and the part still sells 416 GB; Bond's margin is 0.7%. Charged a 1.43% seal ring as well, the one a GPU-size memory die would carry, Grown would hold 418.8 GB user-capable, a 0.7% margin.

#Cost

The tier cost is $3,600 per wafer-tier, a 28 nm-line anchor applied in a leading-edge GPU fab, over 64 GPU sites: $56.25 per die-tier, with tier P counted as one to two tier-equivalents (Eq. 39). It is spent on every site, good or bad.

Costs exclude what §8 lists, plus line-yield scrap over the added levels, with $30k–210k of work in progress at risk per wafer. The host's own cost per wafer-tier is unknown (§8).

Against Bond. Bond's $10.62 per GB sold is per set of six tiles, divided by its 76.4% tile yield and, for the steps on the GPU wafer, by a GPU sort yield of 0.8; Grown's $8.28–8.45 is divided by a GPU yield of 0.8. The two do not compare directly, and the family's rules do not rank them on cost (§8). With tier isolation Bond's tiles cost $9.58 per GB sold against G416's $13.98–14.27 at GPU yield 0.474 (Eq. 7), 0.67–0.69× as much; per good GPU at a yield of 0.8, Grown's own basis, G416 is 1.26–1.28× cheaper, and it matches Bond's $9.58 at a GPU yield of about 0.70 (0.63 against $10.62). Without isolation, counting the GPUs each scraps at $5k–20k, G416 costs $18.3–24.0 against B352's $13.0–35.6 per good stack.

#The configuration, and why G416

Why G416. Grown is chosen by its own rule, not the family's sequence (§11), because it has to do more than Bond. C1: more than Bond's 352 GB sold. C2: bandwidth, the lesser of its array after refresh and its lanes at the 500 MHz design rate, more than Bond's wherever Bond delivers anything, on the published points and the grid above. R1: rated 105 °C at a 20 ns row cycle with refresh duty 50% or less (§3). Then the lowest cost per GB sold per good GPU at a GPU yield of 0.8, then 0.5, then per GPU die. Candidates sit on Bond's 32 GB grid with the fewest data tiers that cover it; G288, below Bond's capacity, is kept for comparison. Only G416 is offered (Eq. 30–32, 38–39):

G448, G480 and G512 fail C2. G512 delivers 10.6 TB/s at 105 °C and 40 ns against Bond's 26.4, and 21.2 against 52.9 at 115 °C and 20 ns; G448 delivers 25.4 against 26.4 at 105 °C and 40 ns. The rule as written would pick G384, 0.4% cheaper per GB sold. We keep G416, a choice, not the rule's result: G384 takes four fewer growth passes on a thermal budget no host has qualified, tolerates the larger GPU-fatal share and keeps the larger margin against Bond (table), but G416 holds 32 GB more. The cap on Grown's data tiers is Bond's own 46: G416's 46 pass C2 and G448's 49 fail it, outside both parts' rating. Two constraints are ours, not the rule's: the 32 GB grid and a capacity margin of about 2%. Off the grid, a 424 GB part on the same 46 tiers passes all three tests and would be 1.9% cheaper, but its margin is 0.3% (a tower field of 4.26% at most) and a 1.43% seal ring would take it below 424 GB (above); a 400 GB part also passes and is only 0.2% cheaper.

What G416 gives up. Against G288: bandwidth and fatal-share tolerance (table above), 44% more refresh power, 14–15 more growth passes, with the growth window at 82–83% of the one-hour anchor against 58–60% (§19), 70–112 more mask levels and 245–588 days of fab time against 175–420, a 2.3% rather than 1.6% tower IR floor, 107 against 76 µm of bow per 10 MPa, a full-capacity bin at the mask-scaled tier yield of 35–65% against 58–82%, and 39% more cost per GPU die. In return it holds 44% more, and more than Bond. It is 3.5% cheaper per GB sold than G288 only if tier isolation works; without isolation it is 0.7% dearer ($9.69 against $9.63 per GB at a GPU yield of 0.8), and per expected GB after downbinning at the mask-scaled tier yield it stays 2.8% cheaper with isolation. Against G448, G480 and G512 it costs 1.5–2.9% more, which buys the bandwidth margin against Bond (G384: above).

The risk. G416 is the only Grown part. Its main risks, the thermal budget, the GPU-fatal share, the defect density of an 800 mm² tier, stack stress and fab time, and the parity behind its bandwidth margin against Bond, are Risks 34 and 35; a smaller Grown part would ease each but retire none. Three test vehicles retire them before any tier touches a GPU wafer (§25).

#21Alternative attachments

The same module, tier P included, can attach to two other kinds of host; neither is the lead.

A backside-powered (A16-class) host. The tiers grow on the GPU's finished front back end before the carrier bond. Backside-power flows bond a carrier onto the front, flip the wafer, thin it and build the power network on the back [75][76], so the tiers ride through the carrier bond, the thinning and the backside steps, re-entering shared bonding, grinding and backside tools, which a copper-style rule forbids without a re-entry check or duplicated tools. In return none of the GPU's current or package I/O crosses the tiers, and the memory rails come from the backside network through feedthroughs; but the stack sits in the heat path, on a die thinned for its power network, where vendors report backside heat roughly doubling [67]. Samsung's analysis of a real backside-powered product sends 93.3% of the heat through the carrier side [77]; we keep 100%, the conservative case. With R″ = h/k at 1.25 W/mm², G416 adds +3.9–6.2 K with thermal columns and +10.7–21.4 K without them (Eq. 43). Holding the junction would cost 7.8–11.7% of GPU power with columns and 18.6–31.4% without, so thermal columns are mandatory here. With no power in the front top metal, option A's sense amplifiers in the GPU (§18) fit this host better than the lead.

A host base die. The tiers grow on the GPU package's trailing-node base die (N6 to N3P class) under the compute die. The memory is tested before the compute die is attached, the required tier yield falls back to the 0.997 basis, and a thermal-budget failure costs a base site, not a GPU. The compute junction pays no stack term, but the memory still runs at about the GPU's junction temperature, so refresh is unchanged, and its own heat now includes the bond link, as Bond's does (§15); crossing one bond, its bandwidth and energy per bit are of Bond's kind, 0.08–0.4 pJ. This attachment has Bond's shape with the sense array in tier P instead of a silicon base; a host would fairly ask why not take Bond and keep 2D chemistry out of its line. With tier P the base die no longer gives 11–27% of its transistors to sense amplifiers, but the compute die's full current still passes through the tiers, as it does through the I/O dies in AMD's MI300 [78]. NVIDIA's Rubin, a 2.5D part on our reading of [11], has no such base die.

Feynman-class GPUs. Growing Van der Waals on a Feynman-class GPU wafer is our design target, not a compatibility claim. NVIDIA has said Feynman will use 3D die stacking and custom HBM [4][5]. It has not said any memory will be grown or bonded on its GPU dies, and has published no die size, power, node or memory interface. It would need NVIDIA and its foundry to run our tier module in their line and add lane landings and memory controllers to the GPU. PhantaField has no relationship with NVIDIA. Feynman is reported to use TSMC A16 (analyst, 28 October 2025 and 1 December 2025; unconfirmed by NVIDIA or TSMC) [9]. If it does, a Feynman-class GPU could take Grown only through the backside attachment above, with its stack in the heat path.

#22What the GPU maker and foundry provide

The GPU maker provides:

• Agreement. A joint development agreement with PhantaField and its foundry.
• Host die. A front-side-powered flip-chip die of the N3/N2 class for the lead attachment.
• Landing grid. A top-metal landing grid and lane receivers for the 4.12 M lanes, to our design kit (§18), and the memory's added rail bumps (§20).
• Memory logic. About 768 channel controllers, a refresh engine fed by its thermal sensors, SECDED, repair and remap tables, MBIST and RAS logging (§18).
• Network. An on-die network and L2 that can absorb what the memory delivers at a 20 ns row cycle, where today's carry less than about 33 TB/s (our estimate, §20), or a decision to cap the memory and place data over the processors that read it.
• Sign-off. Power and signal integrity for the tower drop at the 4× design point, its heat and the GPU power that holds frequency through it (§20).
• Thermal. A plan that keeps the memory at or below 105 °C: the GPU junction under it at or below about 102 °C at 105 °C and a 20 ns row cycle (§20).
• Test. Joint sort, burn-in with a hot-retention screen, and capacity bins with driver support.
• Terms. Who pays for tiers grown on dead GPUs and for GPUs lost to tier defects.

The foundry provides:

• Budget. A contractual time-at-temperature budget for its finished copper/low-k back end, to which the module is qualified (not to NanoGalaxy's 450 °C design basis).
• Requalification. Of that back end and its transistors after the module and bumping (§25).
• Process slot. After the last copper metal and before the pad layer, with the pad layer rebuilt after the tiers.
• Module area. A TMD module area run one way on the copper template, with dedicated NanoGalaxy tools, patterning at 28 nm design rules (193i) for every tier, tier P included, and contamination limits for molybdenum, sulfur and metal-organic residues.
• Capacity. Capacity and fab time for G416's added mask levels (§19).
• Inspection. Tier-by-tier optical inspection and shared defect data, to measure the tier killer-defect density and the GPU-fatal share (at or below 6.8%, §20).
• Stress. A stress and bow budget for the stack, about 10 MPa net or less (§19).
• Design-kit access. So PhantaField can fit the periphery-tier IP, drawn at the tiers' 28 nm design rules, to the host node's top metal.

How Grown is supplied. A process, not a die, under the joint development agreement above, on the pattern of the Everspin–GlobalFoundries MRAM agreement [79]; a module that brings its own tool and new materials cannot be sold as a drop-in licence. Three parts:

1. A process-module licence to the foundry: the tier recipe qualified to the host's limit, the integration flow, the contamination protocol and the qualification data; fees for joint development and qualification, then royalties.
2. NanoGalaxy PP-MOCVD tools and service for the foundry's module area.
3. A design kit for the GPU maker: tier and tower-field rules, the top-metal landing grid, periphery-tier IP, controller RTL for refresh, ECC, repair, remap and MBIST, firmware for bins and refresh grading, and thermal, refresh and yield models.

Who carries what. The host carries the wafer, the yield and the tier cost, which is spent on dead GPUs too (§20). PhantaField carries module development, qualification support and the design kit.

Precedents. All are at mature nodes or inside integrated device makers, and none brought its own deposition tool into an N3, N2 or A16 line. SST licenses SuperFlash to foundries and integrated device makers and reported 75 billion units shipped by December 2016 [80]. Everspin and GlobalFoundries signed a joint development agreement for STT-MRAM in October 2014, amended in 2018 and 2019, sharing 28/22 nm costs with royalties on the MRAM GlobalFoundries makes [79]; UMC and Avalanche followed in August 2018 [81]. Weebit Nano licensed its ReRAM to Texas Instruments in December 2025, about a decade after founding, with no new tool or material class [82]. eMemory's royalties, tied to foundry wafer shipments, were 60.8% of its revenue in the second quarter of 2026 [83]. TSMC's embedded MRAM went from its 2019 paper to NXP automotive samples in 2025 [84], about six years. Grown should be planned as a multi-year co-qualification; it is the furthest out of the three formats.

#23The family side by side

Per GPU die, against a Rubin compute die's share of HBM4 [11], the base of every multiple. Bandwidth is at 95 °C and a 20 ns row cycle unless stated, the limiter in brackets; 40 ns figures at 95 °C. Side is counted at four HBM5-class sites per die, an assumption (§11), and its GB are binary, the others' decimal (Appendix D). Refresh is per GB sold.

#Each format against HBM and custom HBM

• Side fills an HBM5-class site for capacity from one tested die, 64 GB per site and 4.1 TB/s per site through 105 °C at a 10 or 20 ns row cycle (PHY target), below HBM5's stated speed (§10), at about 1.3 times a crude HBM cost proxy (§8), so it sells on capacity and supply, not price.
• Bond is a near tier under the die that coexists with HBM or custom HBM beside it: a bit moved for 6 to 48 times less energy than HBM4 (table above), paid for with its heat in the GPU's budget and the GPU's power path through the tiles (§15), at 1.6× the HBM cost proxy, while hybrid bonding has not reached volume DRAM (SK hynix: HBM5 at the earliest, 23 August 2026 [19]).
• Grown is the largest near tier, 2.9× a Rubin die's 144 GB and more than Bond at the same memory temperature, row cycle and cell retention, with lanes above 119 MHz (§20), but it is a licensed process inside the GPU maker's wafer: capacity is fixed at wafer start, GPU and memory yields multiply, the tiers are grown on untested GPUs, and nothing can be replaced in the field.

#Bond against Grown on the same front-side host

On the junction, Grown's cost overlaps Bond's at low traffic and is lower at high traffic if the tower drop stays near its floor; the two own-heat figures rest on different energy boundaries (Eq. 34).

#Against other stacked memory and 3D DRAM programmes

No 3D DRAM programme, and no DRAM-on-GPU programme, has announced a volume date as of October 2026.

Most 3D DRAM programmes deposit a superlattice and then etch it, 3D NAND style, one lithography step over many layers. Van der Waals is sequential: every tier is grown and fully patterned at 28 nm design rules, so every tier has planar-class density and pays its own patterning, and yield compounds tier by tier unless faults are fenced off (§5–7). Distinct in Bond: 46 data tiers in each tile, so capacity per bonded mm² scales with tiers, not stacked dies, 440 MB per mm² of the GPU's footprint against d-Matrix Raptor's 11.4. Distinct in Grown: the memory needs no bond. Not distinct: DRAM on logic, memory under logic carrying the logic's power (Risk 11), the hot-retention problem, and the cell.

#24What we still have to prove

One register for the family. Shared risks come first; retiring one retires it for all three formats.

#25Roadmap

The roadmap is technical only; the order matters more than any date, because the first four items retire risks for all three formats at once.

1. The cell. An all-MoS₂ 2T0C cell: hot retention and row cycle at 85, 95 and 105 °C and a rail of 1 V or less.
2. The thermal-history twin, the first gate before any tier goes on a GPU (§6), for each format's tier count and base metal: full-flow logic wafers taken through every tier's steps in the real growth and deposition ambient (hydrogen, sulfur and metal-organic precursors, not heat alone), with the dielectric and via-fill steps, plus bump reflow. Afterwards we re-check the host's back end (electromigration, stress migration, dielectric breakdown, via resistance, low-k integrity) and its transistors (threshold, drive current, bias-temperature instability, and SRAM and sense-amplifier offset), and we measure a MoS₂ transistor monitor in tier 1 after the whole stack is built, since the bottom tier sees every later tier's steps; hydrogen moves thresholds and sulfur attacks exposed copper. For Side and Bond the host transistors are the base die's sense amplifiers, PHY and ports; for Grown the GPU's, through the full 49–50-pass sequence, the first of its three pre-product vehicles (items 6 and 7), none a product.
3. A tier-isolation vehicle with injected defects, and a per-tier mask count and cost.
4. S64, the first product, its PHY floorplanned and its port aligned to HBM5 once published, behind the JESD270-4 fallback until then.
5. A Bond vehicle: one 126 mm² tile with a few tiers under a dummy logic die that draws a programmable 299–600 A through its vias, beside a filled band (§16).
6. A few-tier Grown vehicle: a few tiers and tier P with towers on a front-side mature-node logic wafer, measuring the killer-defect density of an 800 mm² tier, the GPU-fatal share, tier isolation, and the tier-P latch and hand-off in 18.6 µm² after a full tier thermal history and bumping, with its row cycle and lane rate, on which the comparison with Bond rests (§20).
7. A full-height Grown vehicle: 48 tiers and tier P on a mature front-side logic host or the GPU maker's engineering N3/N2 wafers, measuring bottom-tier retention after 47 later growth passes, bow, tower IR drop and electromigration, and the fatal share at full height. Bond's tiles carry stack learning across, not the thermal budget of a leading-edge back end (§19).
8. G416 on the first host that signs: a front-side N3/N2-class accelerator, only after the three vehicles. The trailing-node base die of §21 is an alternative attachment of the same module, not an earlier or smaller product.

• Tier-local refresh (second generation). A small MoS₂ sense latch on every tier would let each tier refresh itself, so refresh traffic never touches the vertical lines and duty stops growing with tier count; not committed until such a latch is measured.
• Finer bond pitch. Bond's pad plan already works at TSMC's 4.5 µm target for 2029 (§13).
• A finer base for Side and Bond, which raises Side's pin rate and Bond's lane rate, if its back end meets the tier budget; even a 12 nm-class base would not match the announced 2–3 nm HBM5 base dies (Risk 18).
• Two bits per cell, as upside. It would double Eq. 1 to 220 Mb/mm² but needs several times the single-bit read margin the design leaves at the 0.6 V rail, multi-reference sensing and levels that stay apart through a refresh interval at temperature.
• A cheaper memory tier. The $3,600 adder is an average over the logic and memory tiers of [1]; a single-pass nMOS memory tier may cost less, and the tier adder sets every format's cost floor.
• Finer tiers. With the 8F² cell held, density scales as 1/F², and retention stays roughly the same because node capacitance and leakage both scale with F [1].
• Interface variants for Side: SPHBM4 on organic substrate [57], and UCIe-attached memory, where HBM and LPDDR mappings over UCIe have been shown [58].

#AEquations and worked arithmetic

Symbols: F feature size; N tiers; A area; T temperature; f refresh rate; tRC row cycle; Y yield; h stack height; k thermal conductivity; R″ specific thermal resistance. Results carry the rounding used in the text.

#A.1 Shared

D = 10¹² / (k_cell × F² × (1 + p)) × b
  = 10¹² / (8 × 28² × 1.45) × 1 = 10¹² / 9,094.4 nm² = 109.96 → 110.0 Mb/mm²
check against the Sophon die: 110.0 × 750 × 32 / 8,000 = 330.0 GB
cell area 8 × 784 = 6,272 nm²; raw density 10¹² / 6,272 = 159.4 Mb/mm²; efficiency 110.0 / 159.4 = 69%
MIV slots 1 / (0.09 µm)² = 1.235×10⁸ /mm² · 6 µm bond sites 1 / (6 µm)² = 27,778 /mm² → 4,444×
per-tier density vs Samsung 1b LPDDR5X: 0.110 / 0.436 = 25%

user fraction u = (64/72) × (256/260) = 0.8889 × 0.9846 = 0.8752
Side  : 110.0 × 126 / 8,000        = 1.7325 GB raw · × u = 1.5163 user
Bond  : 110.0 × 640.4 / 8,000      = 8.805 GB raw  · × u = 7.7064 user   (six 126 mm² tiles, 15.29% reserve each; Eq. 22)
Grown : 110.0 × 800 × 0.96 / 8,000 = 10.56 GB raw  · × u = 9.2423 user   (4% tower field; 768 mm² of array)

τ(T) = 1.8 s × 2^(−(T − 25)/10)
  25 °C: 1.8 s · 85 °C: 1.8 × 2⁻⁶ = 28.1 ms · 95 °C: 1.8 × 2⁻⁷ = 14.1 ms · 105 °C: 1.8 × 2⁻⁸ = 7.0 ms
refresh interval: 1 s · 20 ms (28.1 / 20 = 1.4× margin) · 10 ms · 5 ms  → f = 1 · 50 · 100 · 200 Hz
closed form behind τ: τ = C·V_dd / (2·I_off); see §24 row 7 on the per-cell inputs

E_refresh = E_read + E_write = 30 + 20 = 50 fJ/bit
per GB per Hz = 8×10⁹ bit × 50 fJ = 0.4 mW;   P = refreshed raw GB × 0.4 mW × f
refreshed raw GB = data tiers × raw GB per tier (spare tiers are not refreshed):
  S64 46 × 1.7325 = 79.7 · B352 46 × 8.805 = 405.0 · G416 46 × 10.56 = 485.8
S64:  79.7 × 0.4 mW × (1, 50, 100, 200) = 0.032 · 1.59 · 3.19 · 6.38 W = 0.50 · 24.9 · 49.8 · 99.6 mW per GB sold
B352: 405.0 × 0.4 mW × (1, 50, 100, 200) = 0.16 · 8.10 · 16.20 · 32.40 W = 0.46 · 23.0 · 46.0 · 92.1 mW per GB sold
G416: 485.8 × 0.4 mW × (1, 50, 100, 200) = 0.19 · 9.72 · 19.43 · 38.86 W = 0.47 · 23.4 · 46.7 · 93.4 mW per GB sold
per user-capable GB at 105 °C: G416 38.86 / 425.1 = 91.4 mW · B352 32.40 / 354.5 = 91.4 mW · S64 6.38 / 69.75 = 91.4 mW
per GB sold = 0.4 mW × (raw / sold) × f; raw / sold = 1.151 (B352) · 1.168 (G416) · 1.245 (S64, whose 64 GB is a binary 64 GiB)
HBM self-refresh: 10 W / 432 GB = 23 mW per GB to 15 W / 288 GB = 52 mW per GB [1]
DDR5: 32 ms window = 31 Hz [36]; 50 Hz / 31 Hz = 1.6×; 1 s / 32 ms = 31×

duty = data tiers × b_path × f × tRC,   b_path = 110.0×10⁶ / (sense paths per mm²)
  16:1 (Side):        16 × 1,678 = 26,848 /mm² → b_path = 4,097
  8:1 (Bond, Grown):  32 × 1,678 = 53,696 /mm² → b_path = 2,049
at 16:1 (for comparison): B352 and G416 46 × 4,097 × 200 × 2×10⁻⁸ = 75.4% at 20 ns · 151% at 40 ns → 8:1 chosen
rating rules: Side, highest T with duty < 100% and internal × (1 − duty) ≥ 4.10 × 1.125–1.143 = 4.61–4.68 TB/s (Eq. 14) ·
  Bond and Grown, highest T with duty ≤ 50% (Eq. 23, Eq. 32)
refresh twice as often (f = 100 · 200 · 400 Hz): S64 20 ns 151% at 105 °C, 75.4% at 95 °C, 5.20 TB/s left → 95 °C
  B352 20 ns 75.4% at 105 °C, 214.9 × 0.246 = 53 TB/s → 95 °C · B352 40 ns 75.4% at 95 °C → 85 °C
  G416 20 ns 75.4% at 105 °C, 257.7 × 0.246 = 63 TB/s → 95 °C · G416 40 ns 151% at 105 °C, 75.4% at 95 °C → 85 °C
  refresh per GB sold ≈ 46–50 · 92–100 · 184–199 mW at 85 · 95 · 105 °C

c′ × V² = 0.155 fF/µm × 0.36 V² = 0.0558 fJ/µm at 0.6 V
Side : 0.0558 × 16.8 = 0.94 fJ   (S64)
Bond : 0.155 × 16.8 × 0.6² + 0.155 × 25.8 × 0.9² = 0.94 + 3.24 = 4.2 fJ (B352: down the tiers at 0.6 V, then up a data tower
       through the tiers, the 8 µm base back end and 1 µm of bond layer at 0.9 V)
Grown: vertical wire from h + 5 µm to 2h + 15 µm: 0.0558 × (17.15 + 5) = 1.24 to 0.0558 × (34.3 + 15) = 2.75 fJ (G416)
shared-bitline leakage budget: 10% of an assumed 0.1 µA read = 10 nA over the unselected tier-select gates:
  10 nA / 47 = 213 pA per gate (S64's and a B352 tile's 48 tiers; G416's 48 without tier P); their drain overlap and fringe capacitance is not in the figures above

DPW(A) = π × 150² / A − π × 300 / √(2A)
  DPW(126) = 561.0 − 59.4 = 501.6 → 501 · DPW(800) = 88.36 − 23.56 = 64.8 → 64
Y = ((1 − e^(−A·D₀)) / (A·D₀))², D₀ = 0.1/cm²
  126 mm²: ((1 − e^−0.126) / 0.126)² = 0.9396² = 0.8828
  800 mm²: ((1 − e^−0.8) / 0.8)² = 0.4738 (0.6793 at D₀ = 0.05/cm²)

Y_stack = 0.997^N (imec process-control figure via [1]; an assumption)
tier-kill density implied: −ln 0.997 / A_tier = 2.4×10⁻³/cm² (1.26 cm²) · 3.8×10⁻⁴/cm² (8.0 cm²) · Sophon 4.0×10⁻⁴/cm² (7.5 cm²)
area-scaled from Sophon: e^(−4.0×10⁻⁴ × 1.26) = 0.9995 · e^(−4.0×10⁻⁴ × 8.0) = 0.9968
spares: P(≤ s of N fail) = Σₖ₌₀ˢ C(N,k) × 0.003ᵏ × 0.997^(N−k);  P(≤2 of 48) = 0.99958 (S64; a B352 tile; G416 without tier P)

Side       : C_die = ($3,500 + N × $3,600) / 501 / Y_die + $85 = ($6.99 + N × $7.19) / Y_die + $85
Bond       : C_tile = ($3,500 + (N + 2) × $3,600) / 501 / Y_tile + $85;  C_set = 6 × C_tile + 5 × $3,600 / 64 / 0.8   (2 + 5 adders; Eq. 29)
Grown      : C_site = (N_mem + 1 to 2) × $3,600 / 64 = (N_mem + 1 to 2) × $56.25;
  per good GPU = C_site / Y_GPU
$85 = $60 package + $25 test [1] (what it stands for, by format: §8)
$3,600 per wafer-tier ≈ $600 growth and anneal + the rest patterning; no mask count behind it

HBM3E $1.5–1.6/Gb × 8 = $12.0–12.8/GB · HBM4 2H26 $2.0 × 8 = $16/GB · HBM4 2027 proposal ≈ $36–38/GB [48]
DDR5 spot $60.43 / 2 GB = $30.2/GB · contract SO-DIMM $133 / 8 GB = $16.6/GB [49]
commodity cost proxy = $16.6 × (1 − 0.868) = $2.19/GB [51] · HBM cost proxy = × 3 wafer per bit = $6.57/GB [22]

S64 : $545 / 64 GB                   = $8.52
B352: $3,737 / 352 GB                 = $10.62  (six tiles at $564 + $352 of GPU-wafer steps)
G416: $2,756–2,813 / 0.8 / 416 GB     = $8.28–8.45  (per user-capable GB, 425.1: $8.10–8.27)
vs commodity proxy $2.19: 3.89× · 4.85× · 3.78–3.86×;
  vs HBM cost proxy $6.57: 1.30× · 1.62× · 1.26–1.29×
B352 against G416, isolated (Eq. 39): B352's tiles at their isolated 0.8755 plus $85 test each, G416 at 0.4738 with GPU-fatal losses left out: $9.58 · $13.98–14.27 → 0.67–0.69× (one GPU-size Bond die at its isolated 0.4701: $16.73, 1.17–1.20×);
  not isolated, scrapped GPUs at $5k–20k: $13.03–35.56 per good stack, placement and process losses counted · $18.27–23.99;  per good GPU at 0.8: G416 1.25–1.28× cheaper
one basis throughout: per GB sold $8.52 · $10.62 · $8.28–8.45; per user-capable GB $7.82 · $10.54 · $8.10–8.27

Q_crit = ½ × C_node × V_dd = ½ × 0.05–0.2 fF × 0.6 V = 0.015–0.06 fC ≈ 94–375 electrons
C_node = 0.05–0.2 fF fits 8F² at 28 nm, not the 3.0 fF design-basis value (Appendix D). Calculation only.

#A.2 Van der Waals Side

S64: 64 GB = 64 GiB = 2³⁹ bits = 68.72×10⁹ B of user data (HBM densities are binary)
  data tiers = ceil(68.72 / 1.5163) = ceil(45.32) = 46; + 2 spares = 48; user-capable 46 × 1.5163 = 69.75×10⁹ B (65.0 GiB)
  h = 0.35 µm × 48 = 16.8 µm
  43 data tiers (45 built) would hold 65.2×10⁹ B = 60.7 GiB, 5% short of 64 GiB
candidates swept for §11, not offered: 96 GiB, ceil(103.08 / 1.5163) = 68 + 2 = 70 tiers (103.1×10⁹ B, 24.5 µm);
  192 GiB, ceil(206.16 / 1.5163) = 136 + 3 = 139 tiers (206.2×10⁹ B, 48.65 µm)
  HBM4 16-high DRAM silicon: 16 × 30 µm = 480 µm [16]

sense paths = 26,848 × 126 = 3.38 M (0.02% of MIV slots)
internal, in stored bits = 3.38×10⁶ bit / tRC = 42.3 TB/s (10 ns) · 21.1 TB/s (20 ns) · 10.6 TB/s (40 ns)
stored bits read per user bit delivered = (72/64) × (260/256) = 1.143 (1.125 if spare columns are not read)
port need = 4.10 TB/s × 1.125–1.143 = 4.61–4.68 TB/s (HBM5-class port, 4,096 × 8 Gb/s)
duty = data tiers × 4,097 × f × tRC, in % at 85 / 95 / 105 °C:
  S64 (46 data tiers): 10 ns 9.4/18.8/37.7 · 20 ns 18.8/37.7/75.4 · 40 ns 37.7/75.4/151
  candidates (not offered), 20 ns: 68 data tiers 27.9/55.7/111 · 136 data tiers 55.7/111/223
rating = highest T with duty < 100% and internal × (1 − duty) ≥ port need
S64 at 105 °C, 20 ns: 21.1 × (1 − 0.754) = 5.20 TB/s ≥ 4.61–4.68 → 1.11–1.13× → 105 °C
S64 at 40 ns: 95 °C leaves 10.6 × 0.246 = 2.60 < 4.68; 85 °C leaves 10.6 × 0.623 = 6.59 → 85 °C
S64 at 10 ns, 105 °C: 42.3 × 0.623 = 26.3 TB/s
ratings at tRC 10 / 20 / 40 ns: S64 105 / 105 / 85 °C (candidates: 105 / 95 / 85 °C · 95 / 85 / below 85 °C)
limits at 105 °C, 20 ns: data tiers ≤ floor((1 − 4.68 / 21.1) / (4,097 × 200 × 20 ns)) = 47 (54 behind a 2,048-bit port)
  pin rate ≤ 5.20 / 1.143 × 8 / 4,096 = 8.90 Gb/s (9.03 at 1.125) · tRC ≤ 20.5 ns · access efficiency ≥ 1 / 1.11 ≈ 90%
  at 4,096 × 24 Gb/s (12.3 TB/s): rated 85 °C at 20 ns; 105 °C would need tRC ≤ 14.1 ns
if the write-back takes its own cycle (duty charges one tRC per refresh),
  duty doubles (§3's twice-as-often sensitivity): 105 °C at 20 ns 151% → S64 rated 95 °C at 20 ns (5.20 TB/s left ≥ 4.68)
same die, other ports: listed 28 nm IP (1.09–2.18 TB/s) 105 / 105 / 95 °C, 2.08–4.17× · JESD270-4 (2.05 TB/s) 105 / 105 / 95 °C, 2.22×
  a 2,048 × 32 Gb/s port (8.19 TB/s; need 9.36 TB/s): 10 ns 105 °C (26.3 left) · 20 ns 95 °C (13.2 left) · 40 ns below 85 °C (6.59 left)

B = width × r / 8
  4,096 × 8 Gb/s     → 4,096 GB/s = 4.10 TB/s   (HBM5-class target; width and rate from KAIST's projection [103])
  4,096 × 4.267 Gb/s → 2,185 GB/s = 2.18 TB/s       (LPDDR4 PHY IP listed for 28 nm and below, top rate process dependent [54]: an upper bound)
  4,096 × 2.133 Gb/s → 1,092 GB/s = 1.09 TB/s       (DDR3/2 PHY IP listed for 65–28 nm [54])
  2,048 × 8 Gb/s     → 2,048 GB/s = 2.05 TB/s       (the JESD270-4 fallback [13])
HBM4E: 2,048 × 16 Gb/s = 4.1 TB/s (derived; Samsung's sample 3.6 TB/s [109])
KAIST's HBM5: 4.0 TB/s as stated; 4,096 × 8 / 8 = 4.10 TB/s by our arithmetic [103]
draft-based VIP: QDR, 64 pseudo-channels, close to 8 TB/s [119]; up to 32 Gb/s, 32 channels (secondary) [121]
  64 × 32 bits = 2,048 bits; 2,048 × 32 / 8 = 8.19 TB/s (4,096 × 16 / 8 gives the same, so bandwidth alone does not fix the width)
HBM5, Samsung twice HBM4E (1 September 2026) [120]:
  as stack bandwidth: 2 × 3.6–4.1 = 7.2–8.2 TB/s · as pin rate: 2 × 16 = 32 Gb/s, × 4,096 / 8 = 16.4 TB/s (our inference)
HBM5, Samsung 'more than 50%' above HBM4E (27 July 2026) [105]:
  as stack bandwidth: 1.5 × 3.6–4.1 = ≥5.4–6.1 TB/s · as pin rate: 1.5 × 16 = 24 Gb/s, × 4,096 / 8 = 12.3 TB/s (our inference)
S64 against them: 4.10 / 8.2–7.2 = 0.50–0.57× · 4.10 / 16.4 = 0.25× · July: 0.67–0.76×, 0.33×
  listed IP 1.09–2.18 / 8.2–7.2 = 0.13–0.30× (July: 0.18–0.40×)
per GB: 4,096 / 64 = 64 (1,092–2,185 / 64 = 17–34); HBM5 under the stack reading: 7,200 / 80 = 90 to 8,192 / 64 = 128
  (July: 5,400 / 80 = 68 to 6,144 / 64 = 96)

port rate = 4,096 × 8 Gb/s = 3.277×10¹³ bit/s
array read = 3.277×10¹³ × 1.143 × (30 + 0.94) fJ = 1.16 W
PHY at 0.25–1.0 pJ per bit (UCIe-A's 0.25 pJ per bit target [63] to a single-ended 28 nm interposer driver; an assumption, §10)
  = 3.277×10¹³ × 0.25 to 1.0 pJ = 8.2–32.8 W

R = h / (k × A), A = 126×10⁻⁶ m², k = 1–2 W/m·K; heat made in the tiers at 105 °C (refresh + array read)
S64 : 16.8 µm → 0.067–0.133 K/W × (6.38 + 1.16 W) = 0.50–1.0 K

P ≥ 6.38 (refresh, 105 °C) + 1.16 (array) + 8.2 to 32.8 (PHY) = 15.7–40.3 W, before base logic and leakage
I = 15.7 W / 0.9 V = 17.5 A to 40.3 W / 0.7 V = 57.6 A;
  W metal at 5 mA/µm² = 3,490–11,510 µm²;
  at 19.6% fill = 0.018–0.059 mm² = 0.01–0.05% of 126 mm²
signal towers: about 4,096 data, plus command, address, clock and sideband;
  stack-side down, one tower under every bump of the site's ballout (SK hynix HBM4: 16,148 base micro-bumps [53])

S64: Y_die = 0.8828 × 0.997⁴⁸ = 76.42%;  C_die = (6.99 + 48 × 7.19) / 0.7642 + 85 = $460 + $85 = $545 → $8.52/GB
  with isolation: P(≤2 of 48) = 0.99958 → Y_die 88.2% → $484 → $7.56/GB;  wafer processing $3,500 + 48 × $3,600 = $176,300
  45-tier build (43 data, 60.7 GiB): 77.11%, $513; the three added tiers cost $32 per die and 0.7 points of yield
candidates for §11 (not offered), 70 · 139 tiers: Y_die 71.5 · 58.1%; $798 · $1,815 → $8.31 · $9.45/GB
sensitivity ($/GB), S64 (candidates): adder ×2 → 15.6 (15.6 · 18.4); 0.99 per tier → 11.4 (13.0 · 24.4); 0.98 → 17.8 (25.6 · 98.8)
larger outlines, 64 GiB: 136.4 mm², 42 + 2 tiers, 76.56%, $8.50 ($7.61), 1.52–1.55× · 140.8 mm², 41 + 2, 76.46%, $8.60 ($7.72), 1.66–1.68×
  80 GiB first keeps 105 °C at 20 ns on 145.7 mm²: 49 + 2 tiers, 74.29%, $8.40 ($7.36), 1.03×; 64 GiB there $8.71 ($7.84)

cost per GB ∝ (C_base + N × C_tier) / (N × y^N),  y = 0.997
with C_base ≈ C_tier and no fixed cost: d/dN = 0 → N(N + 1) = 1 / (−ln 0.997) = 1 / 0.0030045 → N ≈ 17.8
with the $85 fixed cost and net GB, swept over area and tiers: minimum $7.45/GB at 100 mm² × 64 tiers
  (continuous optimum $7.44 at 110 mm² × 61 tiers);
  the cheapest tier count at every area from 50 to 225 mm², and the cheapest area at every tier count from 28 to 120, within 7%;
  at 126 mm², 30–105 data tiers within 7% (S64's 46: $7.51 per net GB; 68: $7.50; 136: $8.55);
  not every cell: 50 mm² × 28 tiers = $10.41 = 1.40×;  floor set by the tier adder ≈ $5.4/GB

against HBM5 capacity indicators: 64 / (48, 64, 80) = 1.33 / 1.0 / 0.8× (Samsung's stack heights [104] at 32 Gb dies, derived)
  64 / 80 = 0.8× (KAIST [103]);  KAIST 'F400': 400–500 / 8 = 50–62.5 GB per site
package (KAIST's 'F400': four compute dies, eight sites [103]): 8 × S64 = 512 GB at 8 × 4.10 = 32.8 TB/s
  KAIST: 8 × 80 = 640 GB at 8 × 4.0 = 32.0 TB/s as stated (32.8 derived) → 0.8× capacity
  at Samsung's twice HBM4E, stack reading: 8 × 7.2–8.2 = 58–66 TB/s → 0.50–0.57× (July remark: 43–49 TB/s → 0.67–0.76×)
per GPU die, four HBM5-class sites (an assumption; twice Rubin's PHY shoreline): 4 × S64 = 256 GB at 4 × 4.10 = 16.4 TB/s; listed 28 nm PHY IP: 4 × 2.18 = 8.7 TB/s
  two sites, as KAIST's F400 implies (÷ 4): 128 GB at 8.2 TB/s (4.4 on listed IP)
  at tRC 40 ns and 95 °C a site delivers 2.60 / 1.143 = 2.3 TB/s of user data: 9.1 TB/s per die (4.6 at two sites)
no multiple against a Rubin die's HBM4 share (144 GB, 11 TB/s): a different generation

#A.3 Van der Waals Bond

host = 25 × 32 = 800 mm² (assumed; reticle field 26 × 33 = 858 mm² [95])
tile = 12.0 × 10.5 = 126 mm² (Side's outline); DPW(126) = 561.0 − 59.4 = 501.6 → 501; Murphy 0.8828 (Eq. 7)
2 × 3 with 0.1 mm gaps: envelope (2 × 12.0 + 0.1) × (3 × 10.5 + 0.2) = 24.1 × 31.7 = 763.97 mm²
  tiles 756 mm² (94.5%) · gaps 763.97 − 756 = 7.97 mm² (1.0%) · band 800 − 763.97 = 36.03 mm² (4.5%; 0.45 mm by the long edges, 0.15 mm by the short)
vias per tile (Eq. 25): 2 × 30,453 (GPU supply) + 8,334 (GPU I/O, 50,000 / 6) + 2 × 6,791 (own rails) + 2,000 (test) = 84,822
reserve per tile = vias, data towers, their keep-outs and the seal ring = 19.27 mm²
  = 15.29%, exact → array 106.7 mm² per tile, 640.4 mm² per GPU die (one GPU-size die: 13%, 696 mm²)
per data tier: 110.0 × 640.4 / 8,000 = 8.805 GB raw → × 0.8752 = 7.7064 user (1.2844 GB per tile)
B352: ceil(352 / 7.7064) = 46 data + 2 spare = 48 tiers per tile; 354.5 GB user (0.7% margin); 405.0 GB raw refreshed; 58.67 GB per tile
h = 48 × 0.35 = 16.8 µm; tile 50 + 8 + 16.8 + 2 = 76.8 µm, plus a landing metal of a few µm;
  GPU silicon ≈675 + its front wiring 10–15 + tile 76.8 + landing metal ≈3 = 765–770 µm ≤ 775 µm
headroom: 46 data tiers hold 352 GB up to a 15.89% reserve (0.60 points); a 1% round-up to 16% leaves 351.5 GB, B320 at 48 tiers; 47 data + 1 spare keep B352
data tiers to keep 352 GB: every tile sized for 1.15 / 1.3 / 1.5× a corner tile's current → 16.24 / 17.17 / 18.40%, 47 / 47 / 48 ($10.80 / 10.80 / 10.99);
  0.2 mm gaps → 15.41%, 47 ($10.69); a 0.05 mm seal ring → 13.51%, 45; I/O allowance doubled (16,668 per tile) → 16.16%, 47 ($10.80); vias in the band instead (rejected) → 14.98%, 46 ($10.82)

sense paths = 53,696 /mm² × 640.4 = 34.39 M (5.73 M per tile); b_path = 2,049
array = 34.39 M / tRC / 8 = 430 · 215 · 107 TB/s at 10 · 20 · 40 ns
port = 768 channels × 640 lanes = 491,520 × 1 GT/s / 8 = 61.44 TB/s; 80 GB/s per channel
  per tile 128 channels, 81,920 lanes, 10.24 TB/s; port sites 81,920 / 0.65 = 126,031 = 3.6% of a tile's 3.50 M at 6 µm
  per channel 640.4 / 768 = 0.834 mm² and 354.5 / 768 = 462 MB
duty = 46 × 2,049 × f × tRC at 85 / 95 / 105 °C: 9.4 / 18.8 / 37.7% (20 ns) · 18.8 / 37.7 / 75.4% (40 ns)
bandwidth = min(port, array × (1 − duty)):
  20 ns: 61.4 TB/s (194.7 / 174.4 / 133.9 left); slot need 31.6 / 35.2 / 45.9%
    at 105 °C with 90 / 80% of the slots: 61.4 / 61.4 TB/s · at 10 ns, 348.8 − 61.4 = 287 TB/s spare
  40 ns: 61.4 / 61.4 / 26.4 TB/s (port limit at 85 and 95 °C, array limit at 105 °C)
110 / 115 °C (283 / 400 Hz), 20 ns: duty 53.3 / 75.4% → 61.4 / 52.9 TB/s
rating (duty ≤ 50%, as Eq. 32): 105 °C at tRC ≤ 20 ns · 95 °C at 40 ns
vs a Rubin die: 61.4 / 11 = 5.59× · 26.4 / 11 = 2.4×;  per GB 61,440 / 352 = 174.5;  read all of it: 352 / 61.4 = 5.73 ms (Rubin 144 / 11 = 13.1 ms)
requests in flight (Little's law): 61.4 TB/s × 60–100 ns / 64 B = 58k–96k

E = 30 fJ + 0.155 fF/µm × 16.8 µm × 0.6² (0.94 fJ) + 0.155 × 25.8 µm × 0.9² (3.24 fJ) + link = 34.2 fJ + link
  link 0.05 pJ (UCIe-3D target [63])                            → 0.084 pJ per bit
  link 0.37 pJ (d-Matrix, company-reported, incl. datapath [21]) → 0.404 pJ per bit
25.8 µm = 16.8 of tiers + 8 of base back end + 1 of bond layer (the data tower's run at 0.9 V)
vs HBM4 2.4–4 pJ: 2.4 / 0.404 = 5.9 to 4 / 0.084 = 47.5 → '6 to 48 times less'
with an assumed 0.03–0.10 pJ base datapath: 0.114–0.504 pJ → 4.8–35.0× → '5 to 35 times less'

I = 1,000–1,250 W / 0.70 V = 1,429–1,786 A per polarity (0.65 / 0.60 V: 1,923 / 2,083 A); 2.232 A/mm² at 1,786 A
per tile: 2.232 × (126 + 7.97 / 6 + band share), the band shared by edge length: 0.45 × 32 / 3 per tile on a long edge, 0.15 × 24.1 / 2 on a short edge → corner 6.61 mm², middle row 4.80 mm²
  corner 299.0 A (239–299 A) · middle row 294.9 A (236–295 A) · 4 × 299.0 + 2 × 294.9 = 1,785.7 A
5 µm Cu via: 19.63 µm² × 10⁵ A/cm² = 19.6 mA; at half the rule, 299.0 A / 9.82 mA = 30,453 per polarity per tile (every tile sized for a corner)
band: 2.232 × 36.03 = 80.4 A on no vias; it and the edge PHYs' I/O go sideways in the GPU's top metal to the edge tiles' vias (below)
own rails: 300 W / 6 / 0.75 V = 66.7 A per tile → 6,791 per polarity, made from the back onto the base's first metal
J = 299.0 A / (30,453 × 1.963×10⁻⁷ cm²) = 5.0×10⁴ A/cm² → 2.0× at 105 °C (2.5× at 1,429 A); a middle-row tile 2.03×
Black's law (Ea 0.9 eV, n = 2): 1.67× at 110 °C · 1.40× at 115 °C;  1.0× under 2× crowding;  20× against 10⁶ A/cm²
  a tile at 1.15 / 1.3 / 1.5× a corner tile's current: 1.74 / 1.54 / 1.33× at 105 °C · 1.22 / 1.08 / 0.93× at 115 °C
ρ(105 °C) = 1.7 × (1 + 0.0039 × 85) = 2.26 µΩ·cm
R = ρ × [76.8 µm / (30,453 × 19.63 µm²) + bond-pad term] = 2.95×10⁻⁶ Ω per polarity per tile (landing-metal spreading not modeled)
299.0 A → round trip 1.76 mV = 0.25% of 0.70 V · no band path · I²R over the six positions = 2.0–3.1 W
across a gap: q × w² / 8 × R_s over the strip without vias, one 2 µm Cu layer at 105 °C (0.0113 Ω/sq) → 0.96 mV per polarity at its centre
from the die's edge: q × w² / 2 × R_s, fed from one side, w = 0.45 + 0.1 + 0.125 = 0.675 mm → 5.76 mV per polarity at the long edges (0.375 mm → 1.78 mV at the short); 7 such layers bring the long edge to 0.82 mV
vias per GPU die: 6 × 84,822 = 508,932 (365,436 GPU supply, 50,004 GPU I/O, 81,492 own rails, 12,000 test); none in the gaps or the band

C4 at 0.30–0.35 A: 5,102–5,952 per polarity (GPU) · 190–222 per polarity per tile (own rails, 66.7 A), switchable
≈ 2 × 5,952 + 12 × 222 + ≈30,000 I/O (20,000 signals plus grounds) ≈ 44,600 bumps against 800 / 0.15² = 35,556 C4 sites at 150 µm
  → the I/O on micro-bumps at 40–55 µm: a CoWoS-L-class interposer or a substrate with embedded bridges under the I/O
via in 50 µm of silicon: C = 2π × 3.9 ε₀ × 50 µm / ln(3 / 2.5) = 59 fF (5 µm, 0.5 µm liner) · / ln(3.5 / 2.5) = 32 fF (5 µm, 1.0 µm liner); plus the run through the tiers
liner C between the GPU's supply and a tile's substrate: 30,453 × 59 fF = 1.8 nF per tile → a 10 mV step pushes ≈18 pC
vias in the band (rejected, Eq. 22): 2 × 2,048 of 10 µm through ≈77 µm of fill; all I/O there: 36.03 / 0.15² = 1,601 C4 or 36.03 / 0.04² = 22,519 micro-bumps against ≈30,000 I/O bumps
I/O over a tile: 8,334 / 126 = 66 sites and 20,000 / 6 / 126 = 26 signals per mm² → a 2,300-signal HBM PHY would spread over 87 mm²; edge PHYs route inward onto the edge tiles' vias (twice the allowance: Eq. 22)
P(no open in 20,000 single paths at 10⁻⁶) = 0.980

K = 37.5 mm²·K/W / 800 mm² = 0.0469 K/W [1]
61.4 TB/s, 105 °C, 0.05 pJ link: link 4.92×10¹⁴ b/s × 0.05 pJ = 24.6 W + array 16.8 W + refresh 32.4 W + I²R 2.0 W
  + regulator loss (0.75 → 0.6 V) (16.8 + 32.4) × 0.25 = 12.3 W = 88 W → +4.1 K
  + datapath 4.92×10¹⁴ × 0.03–0.10 pJ (15–49 W) + leakage 20–80 W = 123–217 W → +5.8–10.2 K
  0.37 pJ link: 246 W → +11.6 K
22 TB/s at 85 °C: 28–86 W → +1.3–4.0 K; with datapath and leakage 54–183 W → +2.5–8.6 K;  the same traffic through HBM4: 1.76×10¹⁴ × 2.4–4 pJ = 422–704 W
150 W budget → +7.0 K; it holds (150 − leakage − 1.25 × 32.4 − I²R) / (8 × (link + 1.25 × 34.2 fJ + datapath))
  = 61.4 · 61.4 (both port-capped) · 17.8 TB/s on the 0.05 pJ link and 32.2 · 24.4 · 6.4 TB/s on the 0.37 pJ link
  (no · low · high datapath and leakage: none · 0.03 pJ and 20 W · 0.10 pJ and 80 W)
clock hold through the drop: 2 × 0.25% × 1,000–1,250 W = 5.0–6.3 W → +0.24–0.29 K
on-die network: 61.4 TB/s × 8 × 0.087 pJ/(b·mm) = 43 W per mm of mean travel (Eq. 44)

R″ = 16.8 / k_tier + 8 / k_BEOL + 1 / 1.5 + (10–15) / k_GPU-BEOL
  = 13.0 (k = 5, 2, 1.5, 2) to 32.8 (k = 1, 1.5, 1.5, 1.5) mm²·K/W, over the tiles' 756 mm²
61.4 TB/s: 88 / 756 W/mm² × R″ = +1.5–3.8 K · with datapath and leakage +2.1–9.4 K · 150 W: +2.6–6.5 K
GPU junction over the tiles ≤ 105 − 6.51 = 98.49 ≈ 98 °C at 150 W (105 − 2.58 = 102.4 °C at R″ = 13.0)
  61.4 TB/s: ≤ 101.2 °C (target link, 88 W) · 95.6 °C (with datapath and leakage, 217 W) · 94.3 °C (0.37 pJ link, 246 W)
headroom lost at the 98.49 °C cap against a 105 / 110 °C native limit: (105 − 98.49) + 7.0 = 13.5 K · 18.5 K
  → × 800 / 37.5 = 289 · 396 W (uniform flux: an upper bound for a hot-spot-limited GPU)
refresh = 46 × 8.805 GB × 0.4 mW × f (1 / 50 / 100 / 200 Hz) = 0.16 / 8.10 / 16.20 / 32.40 W
  = 0.46 / 23.0 / 46.0 / 92.1 mW per GB sold

tile Y = 0.8828 × 0.997⁴⁸ (0.8657) = 0.7642
isolated: 0.8828 × (1 − 0.003 × 0.0550)⁴⁸ × P(≤2 of 48 fail at 0.003 × (1 − 0.0550)) = 0.8755
  0.0550 = the share of each tier that the through-stack vias and towers take
good tiles per wafer: 501 × 0.7642 = 383 → 63 GPU sets (439 → 73 isolated);  one GPU-size die: 64 × 0.4102 = 26.3
tile wafer = $3,500 + 48 × $3,600 + 2 adders × $3,600 = $183,500 (through-stack vias; bond layer and landing metal)
tile = 183,500 / 501 / 0.7642 + $85 = $564 (isolated $503)
GPU wafer: 5 adders × $3,600 / 64 sites / 0.8 sort yield = $352 per good GPU
  (bonding six tiles; gap fill; thinning and reveal; backside rail vias; backside wiring and bumps; each one tier-equivalent, unsourced)
set = 6 × $564 + $352 = $3,737 → $10.62 per GB sold · isolated $3,372 → $9.58
one GPU-size die (the rejected alternative): $7,349 → $19.14 (isolated $16.73); at 0.981 per tier, $41.35 → tiles 45% · 74% cheaper
per placement, voids scaled by area: y_p = y_800^(126/800) = 0.9968 · 0.9835 · 0.9655 at 0.98 · 0.90 · 0.80; six: 0.981 · 0.905 · 0.810
  published 98% at 70–100 mm², scaled to 126 mm²: 0.964–0.975 per placement
stack yield Y_s = (y_p × y_place)⁶ × e^(−182,718 p) × 0.975, y_place = 0.995–0.99;  e^(…) = 0.998 · 0.982 · 0.833 at p = 10⁻⁸ · 10⁻⁷ · 10⁻⁶
  at p = 10⁻⁷: Y_s = 0.911–0.884 · 0.841–0.816 · 0.752–0.730;  GPU dies lost per good stack (1 − Y_s) / Y_s = 0.10–0.13 · 0.19–0.23 · 0.33–0.37
per good stack = (set / Y_s + (1 − Y_s) / Y_s × GPU value) / 352 = $13.03–35.56 (GPU $5k–20k); one GPU-size die on the same terms $21.57–42.23
  area-only basis (no placement or process term): $11.56–27.98 (one GPU-size die $20.53–38.95)
  four tiles win per good stack at 0.995–0.99 per placement in 6 of 8 cases: $18.26 against $19.44 (0.98, $20k, 0.99)
sensitivity, $ per GB sold (isolated): 0.99 per tier 13.90 (9.79) · 0.985 17.06 (10.04) · mask-scaled 0.989–0.993 (Eq. 38) 14.55 (9.84)
  all adders × 3: 13.26 · GPU-wafer adders × 2 · × 5: 11.62 · 14.61 · GPU sort 0.5: 11.22 · D₀ 0.05: 10.13 · test by tile area: 9.40
  hot retention re-screen after bonding: +0.24 (one $85 insertion per set) to +1.45 (one per tile)
mechanics (Stoney, E′ = 180.5 GPa): sag = 3σ × t_f × r² / (E′ × t_s²)
  tile, 24.8 µm of films on 100 µm of silicon, r = 7.97 mm: 26.2 µm per 10 MPa (6.5 µm at 200 µm); it stands 100 + 24.8 + 2 ≈ 127 µm, ≈130 with the landing metal
  a full-thickness GPU-size die sags 1.7 µm, ≈15× less per MPa, but is too stiff for the bond to flatten
  net stress for a 10 / 15 µm convex sag: 3.8 / 5.7 MPa · a blanket fill of ≈130 µm (the tiles' standing height) at 20–100 MPa on a 775 µm, 300 mm wafer: 1.6–8.1 mm of bow
  placements per GPU wafer: 6 × 64 × 0.8 + 64 × 0.2 = 320 → 9.6–12.0 min at 2,000–1,600 per hour
selection, six tiles: duty at 20 ns and 105 °C ≤ 50% for ≤ 61 data tiers → B128–B448 rated; C1 (below 416 GB) → B128–B384;
  C2 (G416 ahead everywhere) needs ≥ 46 data tiers → B352, B384;  $ per GB sold (isolated) at 48 tiers per tile: B352 10.62 (9.58)
  without the 48, B384 at 50 + 2: 10.42 (9.30); without C1 and C2 as well: B416 10.26 (9.06)
counts at 48 tiers: 4 tiles B352 $10.92 · 6 tiles B352 $10.62 (9.58) · 8 tiles B320 $11.77 · 12 tiles B320 $12.37; reserve 14.53 · 15.29 · 16.06 · 17.20%
  four tiles are 2.9% dearer, outside the 2% tie band, so six hold alone;  no stress moves the pick: 0.99 or 0.985 per tier, mask-scaled tier yield,
  test by tile area, adders, GPU sort, D₀ 0.05 · per good stack, per-placement losses favour four tiles in 6 of 8 cases (shown, not adopted)

#A.4 Van der Waals Grown

G416: data tiers = ceil(416 / 9.2423) = 46 (45 gives 415.9 GB, 0.1 GB short); + 2 spare = 48; + tier P = 49 tiers;
  h = 49 × 0.35 µm = 17.15 µm;  user-capable 46 × 9.2423 = 425.1 GB;  raw 46 × 10.56 = 485.8 GB;  GPU sites per wafer 64 (Eq. 7)
per tier against Bond: 9.2423 / 7.7064 = 1.199 (768 against 640.4 mm² of array; a 4% tower field against a 15.29% via reserve, and no seal rings or gaps)
capacity margin: 416 / 46 = 9.0435 user GB per tier → 10.333 GB raw → 751.5 mm² of array → tower field ≤ 6.06%  (B352's margin 0.7%)
  with a 1.43% seal ring as well (a GPU-size die's): 756.6 mm² of array → 418.8 GB user-capable; path ratio against B352 756.6 / 640.4 = 1.182
sweep for §20 (justification; only G416 is offered), each the fewest data tiers that cover it:
  G192 21 + 2 + 1 = 24 (8.40 µm, 194.1 GB) · G288 32 + 2 + 1 = 35 (12.25 µm, 295.8 GB) · G384 42 + 2 + 1 = 45 (15.75 µm, 388.2 GB)
  G448 49 + 2 + 1 = 52 (18.2 µm, 452.9 GB) · G480 52 + 2 + 1 = 55 (19.25 µm, 480.6 GB) · G512 56 + 2 + 1 = 59 (20.65 µm, 517.6 GB)

sense paths = 53,696 × 768 = 41.24 M  (B352: 53,696 × 640.4 = 34.39 M; ratio 768 / 640.4 = 1.199);
  area per path = 768×10⁶ µm² / 41.24×10⁶ = 18.6 µm²;  b_path = 110.0×10⁶ / 53,696 = 2,049, as in B352
lanes: 4.12 M (≈5,370 per mm²) × 500 MHz (assumed; Sophon's design value) / 8 = 257.7 TB/s
  B352: 491,520 lanes × 1 GT/s / 8 = 61.4 TB/s → 8.4× the lanes, 4.20× the lane-level rate
  lane rate to beat B352's port: 61.44×10¹² × 8 / 4.124×10⁶ = 119 MHz;  at 200 MHz, 103.1 TB/s (smallest ratio 1.199×)
  lane rate to carry 209.2 TB/s (95 °C, 20 ns): 209.2×10¹² × 8 / 4.124×10⁶ = 406 MHz

array = 41.24 M / tRC / 8 = 515 · 258 · 129 TB/s at 10 · 20 · 40 ns;  bandwidth = min(array × (1 − duty), 257.7 TB/s of lanes)
G416 duty = 46 × 2,049 × f × tRC: 9.4 / 18.8 / 37.7% (20 ns) · 18.8 / 37.7 / 75.4% (40 ns), equal to B352's (Eq. 23)
G416 bandwidth at 85 / 95 / 105 °C: 257.7 (10 ns, lanes) · 233.5 / 209.2 / 160.6 TB/s (20 ns) · 104.6 / 80.3 / 31.7 TB/s (40 ns)
  lanes bind only if tRC ≤ 14.5 ns at 105 °C (18.3 ns at 85 °C)
against B352, same memory temperature and tRC: 10 ns 257.7 / 61.4 = 4.20 · 20 ns 233.5, 209.2, 160.6 / 61.4 = 3.80, 3.40, 2.61
  40 ns 104.6 / 61.4, 80.3 / 61.4, 31.7 / 26.4 = 1.70, 1.31, 1.20 · 20 ns at 110 / 115 °C: 120.3 / 61.4, 63.4 / 52.9 = 1.96, 1.20
  smallest over 85–115 °C (0.5 K) × tRC 10–40 ns (1 ns), where B352 > 0: 1.199 at 103 °C, 38 ns (1.199 on the published points; 1.199 to 80 ns; ≥ 1.199 at a shared access efficiency of 0.7–1.0)
  G416's duty equals B352's, so wherever both arrays bind the ratio is 1.199 × (1 − duty_G) / (1 − duty_B) = 1.199, for any shared access efficiency η
  B352's port binds at every published point but 105 °C, 40 ns and 115 °C, 20 ns; there G416 / B352 = 1.31–4.20
  B352's port is a design choice: 491,520 lanes / 0.65 data share / 21.0 M sites on six 6 µm tile faces = 3.6% (G416's 4.12 M lanes would take 18.6% of an 800 mm² face's 22.2 M);
    widened to its own array bandwidth at 95 °C, 20 ns (174.4 TB/s): +113.0 TB/s × 8 × 0.05–0.37 pJ = +45–334 W → +2.1–15.7 K, before its base datapath
cap on data tiers (C2): 41.24 (1 − 2,049·D·x) > 34.39 (1 − 2,049·46·x) at every x = f·tRC where B352 > 0 only if D ≤ 46;
  D = 47 loses near B352's cutoff (109.0 °C, 40 ns); G416 (D = 46) passes at 1.199, G448 (D = 49) fails
  inside B352's rating (B352 duty ≤ 50%), smallest ratio: G448 1.121 · G480 1.043 (101.0 °C, 35 ns)
sweep (justification), bandwidth at 20 ns · 40 ns, 85 / 95 / 105 °C, and smallest ratio to B352:
  G192 247 / 236 / 213 · 118 / 107 / 85;  G288 241 / 224 / 190 · 112 / 95 / 61 (both above G384's);  G384 236 / 213 / 169 · 107 / 85 / 40, 1.279
  G448 232 / 206 / 154 · 103 / 77 / 25.4;  G480 230 / 203 / 148 · 101 / 74 / 19.0;  G512 228 / 199 / 140 · 99 / 70 / 10.6 (G448–G512 below B352's 26.4)
rating (duty ≤ 50%): G416 105 °C at ≤ 20 ns, 95 °C at 40 ns (75.4% at 105 °C, 40 ns); sweep: G192 105 °C at ≤ 40 ns, the rest as G416
vs Rubin die: 209.2 / 11 = 19× · 31.7 / 11 = 2.9×;  per GB 209,200 / 416 = 503 GB/s (B352 174.5);  416 GB / 209.2 TB/s = 2.0 ms
refresh: G416 0.19 / 9.72 / 19.43 / 38.86 W at 25 / 85 / 95 / 105 °C (G288 0.14 / 6.76 / 13.52 / 27.03)

E = 30 fJ + 0.0558 fJ/µm × vertical wire, which runs at least h + 5 µm and at most 2h + 15 µm
  (through the stack at most twice, plus 5–15 µm of GPU back end, assumed)
G416: 30 + 0.0558 × 22.15 = 31.24 to 30 + 0.0558 × 49.3 = 32.75 → 31.2–32.8 fJ
excludes the tier-P latch, GPU receivers, ECC and on-die network

P_mem = traffic × 8 × E + refresh;  ΔT_junction = P_mem / 800 × 37.5   (E = 32.75 fJ)
G416: 22 TB/s, 85 °C:   5.8 + 9.7 = 15.5 W → +0.73 K
      96 TB/s, 95 °C:   25.2 + 19.4 = 44.6 W → +2.09 K
      209.2 TB/s, 95 °C:  54.8 + 19.4 = 74.2 W → +3.48 K
      160.6 TB/s, 105 °C: 42.1 + 38.9 = 80.9 W → +3.79 K
      61.4 TB/s (B352's port), 105 °C: 16.1 + 38.9 = 55.0 W → +2.58 K; with 0.27–1.08 K of towers and 0.54–2.01 K of clock hold (Eq. 36) +3.4–5.7 K (B352: 88 W, +4.1 K; ≈4.4 K with its own 0.24–0.29 K hold)
      257.7 TB/s (lane limit), 105 °C: 67.5 + 38.9 = 106.4 W → +4.99 K (only if tRC ≤ ≈14.5 ns)
memory above the local junction, G416 at 80.9 W = 0.101 W/mm²:
  × 2.5 mm²·K/W (5 µm of BEOL at k = 2) = 0.25 K · × 32.15 (17.15 µm stack + 15 µm BEOL at k = 1) = 3.25 K;
    at 22 TB/s 0.05–0.62 K;  at 61.4 TB/s 0.17–2.21 K (B352: 1.5–3.8 K at 61.4 TB/s);
  at 40 ns, 105 °C (31.7 TB/s, 47.2 W) 0.15–1.90 K
all three terms (own + towers + clock hold): 22 TB/s +1.5–3.8 K · 96 TB/s +2.9–5.2 K · 209.2 TB/s, 95 °C +4.3–6.6 K · 160.6 TB/s, 105 °C +4.6–6.9 K
  (B352 at 22 TB/s: +1.3–4.0 K own heat, +1.6–4.3 K with its hold)

I = 1,333 A (1,000 W / 0.75 V) to 1,786 A (1,250 W / 0.70 V) per polarity
W metal at 5 mA/µm²: 2 × 1,333–1,786 / 5 mA/µm² = 0.53–0.71 mm²;
  fill π × 22.5² / 90² = 0.196 → 2.72–3.64 mm² (0.34–0.46%)
towers at 25 mA (assumed) to 65 mA (the maximum per micropillar in [73]): 2 × 1,333 / 0.065 = 41,025 to 2 × 1,786 / 0.025 = 142,880
tower area with clearance → 4.2–7.1 mm² (0.53–0.89%); 4× oversize 13.7–20.9 mm² (1.7–2.6%)

IR floor = J × ρ × h = 5×10⁵ A/cm² × 10⁻⁵ Ω·cm × 17.15 µm = 8.6 mV per polarity
round trip 17.15 mV = 2.3% of 0.75 V  (sweep: 1.1% at 8.40 µm, 1.6% at 12.25 µm, 2.1% at 15.75 µm)
with a lined via (ρ ≈ 20–30 µΩ·cm) and a via-to-landing contact per tier comparable to the via body: ≈ 2–3× the floor
  → 4.6–6.9% of 0.75 V at minimum size, beyond a GPU's IR budget: ruled out
minimum size, heat on the floor: 1,333 A × 17.15 mV = 22.9 W (30.6 W at 1,786 A) → +1.07–1.44 K
design point, towers 4× oversize: 4.29 mV (0.57%) on the floor; 8.6–12.9 mV (1.14–1.72%) with liner and contacts
  against B352's 1.76 mV through its tiles: 2.4–7.3×
  heat: 1,333 A × 4.29 mV = 5.7 W to 1,786 A × 12.9 mV = 23.0 W → +0.27–1.08 K
GPU power to hold frequency through the drop: 2 × (0.57–1.72%) × 1,000–1,250 W = 11–43 W → +0.5–2.0 K, or ≈1–2% of frequency;
  B352: 2 × 0.25% × 1,000–1,250 W = 5.0–6.3 W → +0.24–0.29 K

I = P / 0.6 V: 15.5 · 74.2 · 80.9 W → 26 · 124 · 135 A;
  bumps at 25–65 mA: 26 / 0.065 = 397 to 135 / 0.025 = 5,396 per polarity

without isolation: 0.997⁴⁹ = 0.8631 → GPU loss 13.7%  (sweep 24 · 35 · 45 tiers: 7.0 · 10.0 · 12.6%)
≤ 1% loss needs 0.99^(1/49) = 0.99980 per tier = 14.6× fewer killer defects
  (G416 tier-kill density 2.6×10⁻⁵/cm² against 3.76×10⁻⁴/cm²)
G416 scrap per good assembly: $450 × (1 / 0.8631 − 1) = $71 · $793 at $5k · $3,172 at $20k (illustrative die values)
with isolation and 2 spares: P(≤2 of 48 fail) = 0.99958
GPU loss ≈ N_total × p × f;
  ≤ 1% needs f ≤ 0.01 / (49 × 0.003) = 6.8% (2.0% at p = 0.01; sweep 13.9 · 9.5 · 7.4% at 24 · 35 · 45 tiers)
G416 at f = 1–4%: 0.15–0.59% · at f = 5%: scrap $3.3 · $37 · $147
tower area as the fatal share, loss = 1 − (1 − p × f)⁴⁹: f = 1.7–2.6% (4× towers) → 0.25–0.38% at p = 0.003, 3.6–8.4% at p = 0.044–0.069;
  f = 4% (the whole field) → 0.59% · 8.2–12.6%
mask-scaled sensitivity: D_tier = 0.1/cm² / 90 levels × 5–8 levels = 5.6–8.9×10⁻³/cm²; Y_tier = e^(−8.0 cm² × D_tier) = 0.956–0.931
  G416 without isolation 0.956⁴⁹ to 0.931⁴⁹ = 0.113–0.031 · P(≤2 of 48 fail) = 0.653–0.351 · f ≤ 0.01 / (49 × 0.044–0.069) = 0.47–0.30%
  downbinned on a 32 GB grid: E[GB sold] = 404.7–393.8 (G288 282.1–274.4); $ per expected GB per GPU die 6.88–7.07 (7.08–7.28)

$3,600 / 64 = $56.25 per die-tier;  tier P = 1–2 tier-equivalents
G416: (48 + 1 to 2) × $56.25 = $2,756–2,813 per GPU die → $6.63–6.76 per GB sold · $6.48–6.62 per user-capable GB
per good GPU: ÷ 0.8 = $3,445–3,516 · ÷ 0.5 = $5,513–5,625 · ÷ 0.4738 = $5,817–5,936
  per GB sold at 0.8 · 0.5 · 0.4738: $8.28–8.45 · $13.25–13.52 · $13.98–14.27;  per user-capable GB at 0.8 · 0.5: $8.10–8.27 · $12.97–13.23
without isolation at 0.8: $2,784 / (0.8 × 0.8631) / 416 = $9.69 (G288 $9.63);  + scrapped GPUs at $5k · $20k: $11.60 · $17.32
  at 0.4738, + scrapped GPUs at $5k–20k: $18.27–23.99 (B352 per good stack: $13.03–35.56)
against B352 (Eq. 11), isolated: $9.58 / $13.98–14.27 = 0.67–0.69 (one GPU-size Bond die: $16.73, 1.17–1.20);  crossover Y_GPU = $6.69 / $9.58 = 0.70 (0.63 against $10.62);  per good GPU at 0.8: $10.62 / $8.28–8.45 = 1.26–1.28
sweep for §20 (justification), per GB sold per good GPU at 0.8 · 0.5 · per GPU die:
  G192 $8.79–9.16 · $14.06–14.65 · $7.03–7.32;  G288 $8.54–8.79 · $13.67–14.06 · $6.84–7.03;  G384 $8.24–8.42 · $13.18–13.48 · $6.59–6.74
  G448 $8.16–8.32 · $13.06–13.31 · $6.53–6.65;  G480 $8.06–8.20 · $12.89–13.12 · $6.45–6.56;  G512 $8.10–8.24 · $12.96–13.18 · $6.48–6.59
  off the grid: G400 $8.26–8.44 (passes) · G424 $8.13–8.29 (passes; tower field ≤ 4.26%) · G432 $8.14–8.30 (fails C2)
wafer: (48 + 1 to 2) × $3,600 = $176,400–180,000 vs ≈$30k N2 [74] = 5.9–6.0×
carrying cost of the added fab time at 10%/yr on ≈$118k–120k of wafer: $7.9k–19.3k per wafer → $0.37–0.91 per GB at 0.8

FEOL: 41.24 M paths × 1–2 µm² = 41–82 mm² = 5.2–10.3% of the die (53,696 × 1–2 µm² = 5.37–10.74% of each mm² of array)
landing sites at 1 / 2 µm pitch: bitlines 53,696 × 1 µm² or 4 µm² per mm² = 5.4 / 21.5% of the sites over the array
  the lead's own lanes (G416): 5,370 × 1 µm² or 4 µm² per mm² = 0.54 / 2.1%, through the top power mesh of a front-side host
53,696 / 27,778 = 1.93× every 6 µm bond site

added mask levels = total tiers × m;
  m = 5 (channel, gate, contacts, one local metal, vias) to 8 (device layer + three local metals);
  IBM's 14 nm eMRAM added 3 [45], a module-integration precedent that reuses the host's transistors, not a floor
  G416 49 × 5–8 = 245–392 (392–490 at 8–10 per tier; sweep: 35 tiers 175–280, 45 tiers 225–360);
    vs ≈90 layers for a whole 3 nm flow [1]: 2.7–4.4×
fab time at 1.0–1.5 days per layer (a rule of thumb): 245–588 days; at 0.5 day per layer as a hot lot, 122–196 days
growth passes = 48 + 1 to 2 = 49–50;  growth window ≈1 min per pass → 49–50 min = 82–83% of the ≈1 h above 400 °C anchor [44]
  (G288 58–60%);  chamber residence ≈4 min per pass → 196–200 min = 3.3× that hour

κ = 6 σ t_f / (M t_s²), M = 180.5 GPa (Si biaxial), t_s = 775 µm;
  bow = κ D² / 8, D = 300 mm
per 10 MPa net stress: 107 µm at 17.15 µm (76 µm at 12.25 µm);  320–534 µm at 30–50 MPa → net stress ≤ ≈10 MPa

R″ = h / k at 1.25 W/mm² (100% of heat through the stack; [77] reports 93.3%)
G416 columns: 17.15 / 5.44 = 3.15 to 17.15 / 3.44 = 4.99 → +3.9–6.2 K (+7.9–12.5 K at 2.5 W/mm²)
G416 dielectric: 8.58–17.15 → +10.7–21.4 K;
  power given up R / (37.5 + R) = 7.8–11.7% · 18.6–31.4%

0.155 pF/mm × 0.75² V² = 0.087 pJ per bit and mm (about ¼ for random data)
at 209.2 TB/s: 209.2×10¹² × 8 × 0.087 pJ = 146 W per mm of mean travel (≈36 W random; B352 at 61.4 TB/s: 43 W)
mean Manhattan distance on a 25 × 32 mm die: (25 + 32) / 3 = 19 mm
in flight at 209.2 TB/s × 60–100 ns / 64 B = 196k–327k requests (B352 at 61.4 TB/s: 58k–96k)
GPU side today, our estimate for an H100-class die: 132 SMs × 128 B per clock × 1.98 GHz = 33.5 TB/s of L1 load bandwidth in all, an upper bound on what the SMs take in; L2 and the on-die network carry less
under a common network cap at or below B352's 61.4 TB/s (port limit): G416 / B352 = 1.000 at every 10 and 20 ns point through 105 °C

#A.5 The family

Rubin per die: 288 / 2 = 144 GB · 22 / 2 = 11 TB/s [11] (NVL72 page: 19.2 / 2 = 9.6)
capacity: Side 4 × S64 = 256 (HBM5-class; no multiple; 128 at two sites) · Bond B352 352 (2.44×) · Grown G416 416 (2.89×; 1.182× B352)
bandwidth: Side 16.4 (8.7 on listed IP; no multiple; 8.2 at two sites) · Bond 61.4 / 11 = 5.59× (worst 26.4 / 11 = 2.4×) · Grown 209.2 / 11 = 19× (31.7 / 11 = 2.9×; against B352 at the same T and tRC 1.20–4.20×)
bandwidth per GB, GB/s per GB: Side 64 (34 on listed IP) · Bond 174.5 · Grown 503 · HBM4 2.05–3.3 TB/s / 36 GB = 57–92
HBM4 energy at 22 TB/s: 1.76×10¹⁴ bit/s × 2.4–4 pJ = 422–704 W [20][21]

#BWhere every number comes from

Kinds: measured, device data shown in a public IEEE seminar deck; design, the published Sophon design basis [1] or a choice made for Van der Waals; assumption, an input not yet backed by measurement or a source; derived, computed in Appendix A; external, a published third-party figure, with its date in the reference list.

#B.1 HBM5, tagged by source kind

HBM5 is unpublished: JEDEC lists it as in development (October 2026), so Side's HBM5 inputs carry their own kinds. JEDEC-published: in a JEDEC document or listing. Vendor-announced: said or shown by the company named. Analyst or roadmap: an academic or analyst projection. Rumor: a report the company has not confirmed, or a reporter's own expectation. Where we compute from them, the result is derived. Current to 18 October 2026.

#CFeynman sources, tagged

Current to 15 October 2026. The next likely official disclosure is GTC 2027. Official: said or shown by NVIDIA. Analyst: supply-chain or analyst reporting. Rumor: speculation reported as such.

#DConsistency notes

Conventions used in this paper, and where they depart from the Sophon design basis [1].

• One part per format. One configuration each, S64, B352 and G416, by the selection sequence of §11 (deltas in §16 and §20); other sizes appear only in the justifying sweeps.
• One tier design, one mask set per footprint. 'One tier design' is not one mask set across formats; each footprint has its own masks (§4).
• Rating rules are stated in §3 and carried with their row cycle in every table (Side Eq. 14; Bond and Grown Eq. 23, Eq. 32). On the duty rule alone S64 would be rated 95 °C at 20 ns.
• Stack conductivity. Every format uses the measured 1–2 W/m·K for the dielectric-only case; the Sophon basis's 24.7 W/m·K is not used, because vias cannot supply the copper fill it assumes.
• Every tier needs the all-MoS₂ cell, because in every format each tier sits over a finished back end (Risk 1).
• Process thermal budget. 'Below 450 °C' holds only on a base PhantaField specifies; Grown, and Side or Bond on a Cu/low-k base, face a ≤400 °C-class requirement (§19).
• Measured-data wording takes one form throughout, and the design-basis sentence is one family sentence, used once.
• Refresh rounding. Family text says about 0.5 / 23–25 / 46–50 / 92–100 mW per GB at 25 / 85 / 95 / 105 °C; format tables keep their own values. Only the ratio of refreshed raw GB to GB sold differs; Side's is highest (1.245) because its 64 GB is binary. Per user-capable GB all three refresh alike: about 0.46 / 23 / 46 / 91 mW at 25 / 85 / 95 / 105 °C.
• Bandwidth limiters. Every bandwidth figure carries its limiter in parentheses: Side's PHY target (4,096 pins at 8 Gb/s, a projected width and rate), Bond's port limit and Grown's array limit after refresh, its lanes limiting only below about 14.5 ns. Bond's 1 GT/s and Side's listed-IP figures are at the 28 nm cost basis (§10, §15).
• Energy boundaries. Each figure is printed with what it covers; only Bond carries an HBM4 multiple, '6 to 48 times less', against 2.4–4 pJ from secondary sources, never as a single multiple.
• Side's GB. Side's 64 GB is binary, 64 GiB, as HBM densities are; Bond's and Grown's GB are decimal (10⁹ bytes). An earlier 45-tier S64 held 60.7 GiB; it is 48 tiers here.
• HBM baselines. Side against HBM5, each fact tagged by source kind and date (§10, B.1), as HBM5-class with no compliance claim; Bond and Grown against shipping HBM4.
• Cost basis. Per GB sold, cost not price, October 2026, each format's exclusions beside it (§8, Eq. 11); Bond and Grown divide by different yields and are not ranked on cost (§20).
• Bond's geometry is stated once, in §12 and Figures 1 and 9; one memory die with the GPU's outline is the rejected alternative (§16).
• Bond's vias and current. Every via sits inside a tile, and the gaps and edge band are fill only. The current is the GPU die's own, not a whole package's, and one tile design is sized for a corner (§14, Eq. 25).
• Soft-error critical charge is computed at the 0.6 V rail on a 0.05–0.2 fF node that fits 8F², not the 3.0 fF design-basis value (Eq. 12).
• Tower IR drop is a bulk-resistivity floor with 2–3× liner and per-tier contact terms beside it, and the GPU power that holds its clocks through the drop is in every junction comparison (Eq. 36).
• Side's cost plateau. An earlier wording, that every point of 50–225 mm² × 28–120 tiers lies within 7% of the $7.45 per GB minimum, was wrong: the cheapest tier count at each area and the cheapest area at each tier count do, and the worst corner is 1.40× (Eq. 20).
• Sophon Rev 4.2 errata that bear on this paper: some IGZO references there are labelled as TMD work; one equation keeps a divisor from a superseded tier count; its refresh equation charges only the read; its critical charge is computed at 1.0 V; and one yield figure is mislabelled. The values used here are restated in Appendix A, and none of these errors is carried into this paper.
• Feynman. Co-packaged optics is NVIDIA's own statement (Kyber scale-up); A16 and SoIC remain analyst reports. That a backside-powered Feynman would not fit Bond as designed is in the Which GPUs note; Grown's Feynman wording is in §21, tied to the backside attachment.

#References

1. PhantaField, Sophon PFG-1: 2D-TMD monolithic 3D AI silicon, whitepaper Revision 4.2, October 2026. The design basis for the cell, tier, density, retention, yield and cost equations used here. /whitepaper. Third-party figures quoted through it: imec SCALE-3D sequential-integration process control and MIV pitch; KAIST TERA Lab HBM roadmap; HBM self-refresh power; TechInsights 28 nm wafer cost. Values used here are restated in Appendix A; Rev 4.2 errata that bear on this paper are listed in Appendix D.
2. Measured results shown in a public IEEE seminar deck, September 2026: a capacitor-less 2T0C cell (a MoS₂ write transistor over a silicon read transistor) and MoS₂ n-type transistors in a stack over a silicon p-FinFET. Summarized in words only.
3. PhantaField, NanoGalaxy PP-MOCVD tool and datasheet: 300 mm, growth below 450 °C. /product/ppmocvd
4. Wccftech, "NVIDIA Feynman GPU gets 3D die stacking, custom HBM," 16 March 2026. https://wccftech.com/nvidia-feynman-gpu-gets-3d-die-stacking-custom-hbm-next-gen-rosa-cpu/
5. heise online, "Nvidia Feynman comes with stacked GPU dies and custom HBM," 17 March 2026 (the 'could exceed 2,000 W' figure is the article's own unsourced estimate). https://www.heise.de/en/news/Nvidia-Feynman-comes-with-stacked-GPU-dies-and-custom-HBM-11214678.html
6. NVIDIA Blog, "NVIDIA GTC 2026: Live Updates on What's Next in AI," live blog, 11–19 March 2026 (Feynman, Rosa, LP40, Kyber copper and co-packaged optics scale-up; Bill Dally paraphrased as exploring stacked DRAM). https://blogs.nvidia.com/blog/gtc-2026-news/
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50. Sohu (republishing 十轮网), citing SemiAnalysis: LPDDR5 contract price about $10 per GB, 6 May 2026 (secondary; unverified). https://m.sohu.com/a/1018715883_506163/
51. Micron Technology, fiscal Q4 2026 results (GAAP gross margin 86.8%), Form 8-K exhibit 99.1, 30 September 2026. https://www.sec.gov/Archives/edgar/data/0000723125/000072312526000018/a2026q4ex991-pressrelease.htm
52. Tom's Hardware, "SK hynix shows 16-Hi HBM4 memory for AI accelerators: 48 GB at 10 GT/s over a 2,048 interface," CES 2026, January 2026 (package about 10.5 × 12.0 mm, which it says matches HBM3/HBM3E). https://www.tomshardware.com/tech-industry/sk-hynix-shows-16-hi-hbm4-memory-for-ai-accelerators-48-gb-at-10-gt-s-over-a-2-048-interface; eeNews Europe, "JEDEC preps finalization of HBM4 standard," 15 July 2024 (HBM4 has a larger physical footprint than HBM3). https://www.eenewseurope.com/en/jedec-preps-finalization-of-hbm4-standard/
53. ServeTheHome, "SK hynix HBM packaging at Hot Chips 2026," 23 August 2026 (12.4 × 11 mm and 12.8 × 11 mm HBM4 footprints; 775 µm height). https://www.servethehome.com/sk-hynix-hbm-packaging-at-hot-chips-2026/
54. Synopsys DDR and LPDDR PHY IP listings, read October 2026 (LPDDR4 multiPHY up to 4,267 Mb/s for 28 nm and below, maximum rate process dependent; DDR3/2 PHY up to 2,133 Mb/s for 65–28 nm). https://www.synopsys.com/zh-cn/designware-ip/interface-ip/ddr.html; https://www.synopsys.com/designware-ip/interface-ip/ddr/lpddr4-multiphy.html
55. SK hynix, mass production of 12-layer HBM3E at 9.6 Gb/s, press release 26 September 2024, via HPCwire (27 September 2024). https://hpcwire.com/off-the-wire/sk-hynix-begins-mass-production-of-12-layer-hbm3e
56. HBM base-die processes: TrendForce, 2024. https://trendforce.com/news/?p=9312; TrendForce on TSMC C-HBM4E base dies, 1 December 2025. https://www.trendforce.com/news/2025/12/01/news-tsmc-unveils-custom-c-hbm4e-details-n3p-logic-dies-reportedly-target-2x-efficiency-gain/
57. JEDEC SPHBM4 (JESD330-4) announcement, via Business Wire reprint, July 2026. https://www.01net.it/new-jedec-sphbm4-standard-enables-hbm4-class-bandwidth-on-organic-substrates/
58. UCIe Consortium, UCIe 3.0 specification, via StorageNewsletter, 7 August 2025. https://www.storagenewsletter.com/2025/08/07/fms-2025-ucie-consortium-introduces-3-0-specification-with-64gt-s-performance-and-enhanced-manageability/; Converge Digest on HBM and LPDDR mappings over UCIe, Hot Interconnects 2025. https://convergedigest.com/hoti25-ucie-brings-on-package-memory-to-the-forefront/
59. Z. Huang and Z. Cheng (Peking University), MRS Spring Meeting 2026, session EL12.09.07, 29 April 2026: layer-resolved thermal measurements (TDTR) of interconnect stacks on six chips from 28 nm to 3 nm, most layers about 1–2 W/m·K. https://www.mrs.org/meetings-events/annual-meetings/archive/meeting/presentations/view/2026-mrs-spring-meeting/2026-mrs-spring-meeting-4505591; companion paper: Z. Huang, Y. Sun, T. Jia, R. Wang and Z. Cheng, "Predictive structure to thermal conductivity modeling framework for BEOL interconnect stacks in advanced technology nodes enabled by extensive layer resolved thermal measurements," arXiv 2609.20379, 17 September 2026. https://arxiv.org/abs/2609.20379
60. R. Chen et al. (imec), "Opportunities of chip power integrity and performance improvement through wafer backside connection," EasyChair Preprint 9239, 4 November 2022 (face-to-face wafer-on-wafer stack with the backside-powered die at the bottom and a low-power die such as SRAM cache on top). https://easychair.org/publications/preprint/m5KvR
61. Intel Foundry, 18A-PT base die with backside power, TSVs and a hybrid-bonding interface for 3DIC, HPC/AI brief, November 2025. https://www.intel.com/content/www/us/en/foundry/process/18a.html
62. AMD, 3D V-Cache, IMAPS 18th International Conference on Device Packaging, March 2022 (9 µm minimum TSV and hybrid-bond pitch). https://imapsource.org/article/90014.pdf; TechPowerUp, "AMD Details its 3D V-Cache Design at ISSCC," February 2022 (first generation: 8,192 TSV connections at a 9 µm pitch). https://www.techpowerup.com/292256/amd-details-its-3d-v-cache-design-at-isscc; TechSpot, Ryzen 7 9800X3D review, November 2024 (second generation, cache under the cores; AMD's claim of up to 46% lower thermal resistance). https://www.techspot.com/review/2915-amd-ryzen-7-9800x3d/; Chips and Cheese, "AMD's 9800X3D: 2nd generation V-Cache," 6 November 2024. https://chipsandcheese.com/p/amds-9800x3d-2nd-generation-v-cache
63. UCIe Consortium, UCIe 2.0 with UCIe-3D for hybrid bonding, 6 August 2024. https://www.uciexpress.org/specifications; D. Das Sharma, "Updates on UCIe technology," SNIA SDC 2024 (UCIe-3D targets: up to 4 GT/s per lane, about 0.05 pJ/bit; UCIe-A and UCIe-S power-efficiency targets 0.25 and 0.5 pJ/bit). https://snia.org/sites/default/files/2025-05/SNIA-SDC2024-DasSharma-Updates-on-UCIe-Technology.pdf
64. Tom's Hardware, "The current state of hybrid bonding in 2026," 2 September 2026 (bonder throughput, face-to-face and face-to-back signal densities, Foveros Direct, Adeia v. AMD). https://www.tomshardware.com/tech-industry/semiconductors/hybrid-bonding-roadmap-examined; eeNews Europe, TSMC SoIC roadmap (6 µm today, down from 9 µm; 4.5 µm by 2029), 29 April 2026. https://www.eenewseurope.com/en/tsmc-soic-roadmap-2029-chip-stacking
65. P. Garrou, "IFTLE 475: EPTC 2020: IME on hybrid bonding challenges," 3D InCites, 1 February 2021 (Cu roughness below 1 nm; oxide below 0.4 nm target, 0.5 nm maximum; Cu dishing 5–10 nm). https://www.3dincites.com/?p=65773
66. Converge Digest, "Broadcom ships first 2 nm 3.5D face-to-face compute SoC for Fujitsu," 26 February 2026. https://convergedigest.com/broadcom-ships-first-2nm-3-5d-face-to-face-compute-soc-for-fujitsu-ai-processor/; The Register, "Fujitsu taps Broadcom's 3D chip tech for 144-core Monaka CPU," 27 February 2026 (2 nm compute chiplets stacked on 5 nm SRAM tiles). https://www.theregister.com/2026/02/27/fujitsu_taps_broadcom/
67. SemiEngineering, "Backside power delivery adds new thermal concerns," March 2024 (Ansys and Intel). https://semiengineering.com/backside-power-delivery-adds-new-thermal-concerns
68. Herald Business, SK hynix on the hybrid-bonding yield bar (90–98%), 20 September 2026. https://biz.heraldcorp.com/article/10878775
69. IBM, "Copper interconnects" (introduction of copper wiring, 1997). https://www.ibm.com/history/copper-interconnects; H. Hogan, "Contamination concerns dull copper's benefits," Solid State Technology, via Semiconductor Digest (IBM's Shahidi: fabrication split into two areas, wafers never returned across the copper line, tools duplicated where needed). https://sst.semiconductor-digest.com/?p=43035
70. Silicon Semiconductor, Lam Research ALTUS Halo molybdenum ALD, February 2025. https://siliconsemiconductor.net/article/121172/Lam_Research_ushers_in_new_era_of_semiconductor_metallisation_
71. Futurum Group on Applied Materials Spectral molybdenum contacts, February 2026 (vendor claim; no fab named). https://futurumgroup.com/insights/will-applied-materials-transistor-breakthroughs-empower-2nm-ai-chips/
72. IEEE IRDS 2024, Yield Enhancement chapter (no published limits for sulfur, chalcogen or metal-organic residues). https://irds.ieee.org/images/files/pdf/2024/2024IRDS_YE.pdf; EAG Laboratories, "The total solution for surface contamination measurements" (TXRF detection limits 10⁹–10¹⁰ atoms/cm² for most metals). https://eag.com/app-note/the-total-solution-for-surface-contamination-measurements; Measurlabs, "Vapour phase decomposition ICP-MS" (VPD-ICP-MS 10⁶–10¹⁰ atoms/cm²; TXRF 10⁹–10¹²). https://www.measurlabs.com/methods/vapour-phase-decomposition-icp-ms
73. US Patent 9,397,073 B1, GlobalFoundries, filed 23 March 2015, issued 19 July 2016 (maximum current load about 65 mA per micropillar; the 25 mA lower bound used here is our assumption). https://patents.google.com/patent/US9397073
74. Tech Insider, TSMC 2 nm wafer price 2026, 7 August 2026 (about $30k, relaying Tom's Hardware, with TrendForce corroborating; TSMC does not publish prices). https://tech-insider.org/tsmc-2nm-wafer-price-2026/
75. IEEE Spectrum, S. K. Moore, Intel PowerVia backside power process order, 8 June 2023. https://spectrum.ieee.org/backside-power-delivery
76. imec, "How to power chips from the backside," 25 November 2022. https://www.imec-int.com/en/articles/how-power-chips-backside
77. D. Shin et al. (Samsung Electronics), "Device-to-package level thermal risk analysis of the back-side power delivery network," SISPAD 2025. https://in4.iue.tuwien.ac.at/pdfs/sispad2025/SISPAD2025_059.pdf
78. W. Lambert (AMD), "Heterogeneous Integration in High Volume: Now and Looking Forward," IMAPS Device Packaging Conference 2025, Phoenix (MI300 I/O base dies, 3D hybrid bonding). https://imapsource.org/article/147811.pdf
79. Everspin–GlobalFoundries STT-MRAM joint development agreement (17 October 2014), Amendment No. 4, effective 31 December 2019 (12LP cost sharing and royalty schedule), SEC exhibit. https://www.sec.gov/Archives/edgar/data/1438423/000155837021002369/mram-20201231xex10d11d4.htm; Amendment No. 3, effective 1 January 2018 (28/22 nm cost sharing, royalty reduction), FY2018 Form 10-K Exhibit 10.27. https://www.sec.gov/Archives/edgar/data/1438423/000155837019002175/mram-20181231ex10276b5d5.htm; Design & Reuse, 12 nm extension, March 2020. https://us.design-reuse.com/news/47676/everspin-globalfoundries-mram-12nm.html
80. Microchip Technology, "SST announces shipment milestone of 75 billion units with embedded SuperFlash technology," December 2016. https://www.microchip.com/en-us/about/news-releases/corporate/sst-announces-shipment-milestone-of-75-billion-units-with-embedded-superflash-technology; SST (Microchip), SuperFlash licensing. https://www.sst.com/about
81. UMC and Avalanche Technology, 28 nm embedded MRAM partnership, 6 August 2018. https://www.umc.com/en/News/press_release/Content/technology_related/20180806
82. Weebit Nano, half-year results and Texas Instruments licence, 27 February 2026. https://www.weebit-nano.com/news/press-releases/weebit-nano-achieves-record-half-year-revenue-licenses-reram-to-tier-1-texas-instruments/
83. eMemory Technology, Q2 2026 results (third-party summary). https://quartr.com/events/ememory-technology-inc-3529-q2-2026_F9xtBHy3
84. NXP and TSMC, 16 nm FinFET embedded MRAM for automotive, 16 May 2023 (samples early 2025). https://www.nxp.com/company/about-nxp/newsroom/NW-NXP-AND-TSMC-DELIVER-FIRST16NM-FINFET-MRAM
85. SemiAnalysis, "NVIDIA: the inference kingdom expands," 24 March 2026 (paywalled; LP40 hybrid-bonded DRAM plans). https://newsletter.semianalysis.com/p/nvidia-the-inference-kingdom-expands
86. imec, HBM-on-GPU and DRAM-on-GPU thermal study, ESSERC 2026, arXiv 2609.24343, 21 September 2026. https://arxiv.org/abs/2609.24343
87. Stanford Engineering, "Scientists and US foundry achieve 3D chip breakthrough" (IEDM 2025, with SkyWater), 10 December 2025. https://engineering.stanford.edu/news/scientists-and-us-foundry-achieve-3d-chip-breakthrough-accelerate-ai
88. SEL, 1-Mbit 3D DRAM with oxide-semiconductor FETs stacked on Si CMOS, IEEE Journal of the Electron Devices Society 12, 236–242, 2024 (over 99% of data retained after 1 h at 85 °C without refresh). https://doaj.org/article/936c403535f14b428f2a5a71bfb5a0ef
89. Samsung 3D DRAM roadmap: KED Global, April 2024. https://www.kedglobal.com/newsView/ked202404020016; Digitimes, 28 May 2024. https://www.digitimes.com/news/a20240528PD209.html; Samsung, "Ongoing Evolution of DRAM Scaling via Third Dimension – Vertically Stacked DRAM," 2023 Symposium on VLSI Technology and Circuits, paper TFS1-1. https://ieeexplore.ieee.org/document/10185290
90. SemiWiki repost of Asia Business Daily, "DRAM faces unprecedented demand; 3D evolution opens a new chapter," 24 January 2026. https://semiwiki.com/forum/threads/chip-talk-dram-faces-unprecedented-demand-3d-evolution-opens-a-new-chapter.25550/
91. Kioxia, OCTRAM, 10 December 2024. https://www.kioxia.com/en-jp/about/news/2024/20241210-1.html; Kioxia, 8-layer stacked OCTRAM, 12 December 2025. https://www.kioxia.com/en-jp/about/news/2025/20251212-1.html
92. NEO Semiconductor 3D X-DRAM proof of concept, StorageNewsletter, 13 May 2026 (company claims). https://www.storagenewsletter.com/2026/05/13/neo-semiconductor-demonstrates-3d-x-dram-proof-of-concept-secures-strategic-investment-to-advance-ai-memory/; StorageNewsletter, "NEO Semiconductor unveils 1T1C and 3T0C IGZO-based 3D X-DRAM technology," 8 May 2025 (cell types; simulation claims). https://www.storagenewsletter.com/2025/05/08/neo-semiconductor-unveils-1t1c-and-3t0c-igzo-based-3d-x-dram-technology/
93. SoftBank, SAIMEMORY and Intel Z-Angle Memory agreement, 3 February 2026. https://www.softbank.jp/en/corp/news/press/sbkk/2026/20260203_01/
94. Loo et al. (imec), 120 Si₀.₈Ge₀.₂/Si bilayers for 3D DRAM, Journal of Applied Physics 138, 055702, 2025. https://doi.org/10.1063/5.0260979
95. ASML, TWINSCAN NXE:3600D (26 × 33 mm exposure field). https://www.asml.com/en/products/euv-lithography-systems/twinscan-nxe-3600d
96. Wccftech, Feynman on NVIDIA's GTC 2025 roadmap, 18 March 2025. https://wccftech.com/nvidia-next-gen-feynman-gpu-updated-roadmap-arriving-2028-next-gen-hbm-memory/; TrendForce, 19 March 2025. https://www.trendforce.com/news/2025/03/19/news-gtc-2025-nvidia-unveils-more-on-rubin-gpus-announces-feynman-for-2028-in-roadmap-update/
97. Wccftech, Feynman with Groq LPU units (analyst AGF speculation), 28 December 2025. https://wccftech.com/nvidia-feynman-gpus-could-see-the-inclusion-of-groq-lpu-units-by-2028/
98. igor'sLAB, relaying DigiTimes (28 January 2026), on Feynman and Intel Foundry. https://www.igorslab.de/en/nvidia-feynman-and-intel-foundry-new-report-old-core-but-with-important-packaging-clue/
99. TrendForce, NVIDIA reportedly eyes small-scale HBM base die production in 2027, 18 August 2025. https://www.trendforce.com/news/2025/08/18/news-nvidia-reportedly-eyes-small-scale-hbm-base-die-production-in-2027-rattling-memory-chip-markets/
100. Gigazine, "TSMC unveils its process roadmap through 2029, adding A13 and A12," 23 April 2026 (TSMC's North America Technology Symposium, 22 April 2026: A14 from 2028 without backside power; its Super Power Rail successor, earlier announced as an A14 variant for 2029, named A12). https://gigazine.net/gsc_news/en/20260423-tsmc-roadmap-a13/
101. Samsung Electronics Newsroom, "Samsung showcases AI-era vision and latest foundry technologies at SFF 2024," 12 June 2024 (SF2Z with a backside power delivery network, mass production slated for 2027). https://news.samsung.com/global/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024
102. JEDEC, 'Main Memory: DDR SDRAM, HBM' technology focus area (HBM5 listed as in development in JC-42.2, beside DDR6), and the JEDEC HBM standards index (newest document JESD270-4A, December 2025), read through a search index on 18 October 2026 because jedec.org refused direct requests. JEDEC-published status. https://www.jedec.org/category/technology-focus-area/main-memory-ddr-sdram; https://www.jedec.org/standards-documents/results/HBM
103. KAIST TERA Lab (Prof. Joungho Kim), HBM roadmap to HBM8, presented 11 June 2025: Wccftech, 14 June 2025 https://wccftech.com/next-gen-hbm-architecture-detailed-hbm4-hbm5-hbm6-hbm7-hbm8-up-to-64-tbps-bandwidth-240-gb-capacity-per-24-hi-stack-embedded-cooling/; 3DInCites, IFTLE 635, 30 July 2025 (120 W per HBM5 stack, against 100 W elsewhere) https://www.3dincites.com/2025/07/iftle-635-kaist-tera-hbm-roadmap/; Blocks & Files, 26 June 2025 (the 'F400' projection) https://blocksandfiles.com/2025/06/26/four-more-hbm-generations/. Analyst or roadmap.
104. Seoul Economic Daily, 'Samsung unveils first HBM5 mock-up with 2 nm base die,' 1–2 June 2026 (mass production 'around 2028' is the reporter's expectation) https://en.sedaily.com/finance/2026/06/01/samsung-unveils-first-hbm5-mockup-with-2-nm-base-die; The Elec, 3 June 2026 https://www.thelec.net/news/articleView.html?idxno=10996. Vendor-announced.
105. TrendForce, 'Samsung reportedly eyes 2 nm base die for HBM5,' 18 March 2026 (GTC remarks) https://www.trendforce.com/news/2026/03/18/news-samsung-reportedly-eyes-2nm-base-die-for-hbm5-1d-dram-for-hbm5e-hbm4-to-exceed-50-of-output/; EDAILY, 27 July 2026, on Samsung Newsroom (2 nm GAA base die; HBM5 'expected to require an operating speed increase of more than 50%' over HBM4E) https://en.edaily.co.kr/news/eda202607275173/. Vendor-announced.
106. XenoSpectrum, Samsung zHBM at FMS 2026, August 2026 (reports a 4,096-bit, ~4 TB/s HBM5 target), checked against Samsung's FMS 2026 tech-blog post, which carries no such figure. Rumor. https://xenospectrum.com/en/samsung-zhbm-vertical-memory-stack-fms-2026/; https://semiconductor.samsung.com/news-events/tech-blog/samsung-presents-its-vision-for-next-generation-ai-infrastructure-with-3d-memory-architecture-at-fms-2026/
107. Samsung Newsroom, 'Samsung unveils next-gen 3D memory vision at FMS 2026,' 4 August 2026 https://news.samsung.com/global/samsung-unveils-next-gen-3d-memory-vision-at-fms-2026-charting-the-future-of-ai-infrastructure; Korea Times, Samsung at the OCP Global Summit, 13 October 2026 https://www.koreatimes.co.kr/business/companies/20261013/samsung-showcases-next-generation-ai-memory-at-ocp-highlights-amd-partnership. Vendor-announced.
108. TrendForce, SK hynix roadmap at the SK AI Summit (3 November 2025), 4 November 2025 https://www.trendforce.com/news/?p=47756; SK hynix press release, iHBM, 25 May 2026, via TrendForce, 'SK hynix introduces iHBM,' 26 May 2026 https://www.trendforce.com/news/2026/05/26/news-sk-hynix-introduces-ihbm-solution-targets-hbm5-adoption-with-30-thermal-resistance-reduction/. Vendor-announced.
109. Samsung Newsroom, 'Samsung begins shipment of industry-first HBM4E samples,' 29 May 2026 https://news.samsung.com/global/samsung-electronics-begins-shipment-of-industry-first-hbm4e-samples; TrendForce, 'SK hynix ships 12-high HBM4E samples,' 18 June 2026 https://www.trendforce.com/news/2026/06/18/news-sk-hynix-ships-12-high-hbm4e-samples-boosts-bandwidth-to-16gbps-and-power-efficiency-by-over-20/. Vendor-announced.
110. Rambus, HBM4E controller IP at 16 Gb/s, 4 March 2026 https://www.rambus.com/rambus-sets-new-benchmark-for-ai-memory-performance-with-industry-leading-hbm4e-controller-ip/; EE Times, GUC 2 nm 16 Gb/s HBM4E IP, September 2026 https://www.eetimes.com/guc-announces-2nm-16-gbps-hbm4e-ip/. Vendor-announced; no HBM5 PHY or controller IP found through 18 October 2026.
111. NVIDIA blog, NVLink Fusion and NVHBM custom high-bandwidth memory, 26 August 2026. Vendor-announced. https://blogs.nvidia.com/blog/nvlink-fusion-nvhbm-custom-high-bandwidth-memory/
112. Crypto Briefing, NVHBM base dies on TSMC 3 nm, 18 October 2026 (no source named; NVIDIA's own 3 nm HBM base die was first reported on 18 August 2025 [99]). Rumor. https://cryptobriefing.com/tsmc-nvidia-custom-hbm-base-dies/
113. TrendForce, custom HBM4E timelines (HBM4E 2027, HBM5 2029), 23 January 2026 https://www.trendforce.com/news/2026/01/23/news-samsungs-custom-hbm4e-design-reportedly-aimed-for-mid-2026-parallels-sk-hynix-and-micron/; TrendForce, HBM generations every 2–2.5 years (Advantest), 1 September 2025 https://www.trendforce.com/news/2025/09/01/hbm-evolution-outpaces-jedec-standards-as-generation-cycles-shrink-to-2-5-years/. Rumor (industry expectations relayed from The Elec); the cadence is vendor-announced (Advantest).
114. TrendForce, Micron HBM4E ramp with TSMC logic dies in 2027, 22 May 2026 https://www.trendforce.com/news/2026/05/22/news-micron-turns-more-upbeat-on-outlook-reportedly-sets-2027-hbm4e-ramp-with-tsmc-for-standard-and-custom-logic-dies/; TrendForce, Micron earnings preview (first HBM4E to follow 'the JEDEC standard'), 22 June 2026 https://www.trendforce.com/news/2026/06/22/news-micron-earnings-preview-four-key-areas-in-focus-hbm-progress-capex-and-more/. Vendor-announced; no published HBM4E standard found against the JEDEC index [102].
115. TrendForce, Samsung dummy-die patent seen as aimed at 16-layer HBM5 (industry estimates of 40–60% yield for 16-layer stacks), 2 July 2026. Rumor. https://www.trendforce.com/news/2026/07/02/news-samsung-files-new-hbm-dummy-die-patent-to-enhance-high-stack-reliability-seen-as-aimed-at-16-layer-hbm5/
116. Wccftech, Samsung's hybrid-bonded HBM reportedly in 2029, 21 July 2026 https://wccftech.com/samsung-delays-hybrid-bonding-hbm-to-2029-aligning-next-gen-memory-with-nvidias-feynman-ai-gpus/; Herald Business, 20 September 2026 https://biz.heraldcorp.com/article/10878775. Rumor.
117. The Register, AMD Instinct MI500 with HBM4E, 7 January 2026 (CES keynote, 5 January 2026). Vendor-announced. https://www.theregister.com/2026/01/07/mi500x_amd_ai/
118. TrendForce, relaying Wccftech on Feynman's memory ('a custom-enhanced HBM4E or a fully bespoke HBM5'), 17 March 2026. Rumor. https://www.trendforce.com/news/?p=54621
119. Synopsys blog, 'Fast-Track Design Verification for AI Accelerators, GPUs & HPC Designs with HBM5 Verification IP,' August 2026, read through a search index on 18 October 2026; the page now returns 404. Its references cite 'JEDEC HBM5 Draft version 1.0-04'; it describes QDR signalling, 64 pseudo-channels and bandwidth approaching 8 TB/s per stack. Vendor-announced. https://www.synopsys.com/blogs/chip-design/ai-accelerators-hbm5-verification-ip.html
120. TrendForce, Samsung's memory roadmap at SEMICON Taiwan (HBM5 targets twice HBM4E's performance), 1 September 2026 (Jangseok Choi, Memory Product Planning, at SEMICON Taiwan, via Newspim; zHBM's 8× and 3× given against HBM4E). Vendor-announced. https://www.trendforce.com/news/2026/09/01/news-samsung-unveils-memory-roadmap-at-semicon-hbm5-targets-2x-hbm4e-performance-zhbm-8x-boost
121. PC Central, report on Synopsys's HBM5 verification IP, 31 August 2026 (up to 32 Gb/s per pin with QDR signalling, up to 32 channels and 64 pseudo-channels; no primary link). Rumor. https://pccentral.net/synopsys-hbm5-verification-ip-ships-memory-bandwidth-approaches-8-tb-s/
122. Cadence HBM3E PHY IP for TSMC N7 (up to 8.0 Gb/s per pin) and N5P (up to 8.4 Gb/s per pin), Design & Reuse listings, read October 2026. Vendor-listed. https://design-reuse.com/sip/high-bandwidth-memory-hbm3e-3-phy-for-tsmc-n7-ip-55816; https://design-reuse.com/ip/view/prod223/high-bandwidth-memory-hbm3e-phy-for-tsmc/