The PFG-1 Sophon IP solution launches — 330 GB of DRAM inside the compute array, 4.2 PB/s of weight bandwidth, one die that trains and serves an 80B model.
Fetching a weight across a package costs more than the math it feeds. The fix isn't faster memory — it's shorter wires.
The memory wall is the growing gap between how fast a chip can compute and how fast it can move data from memory. Here is what it is, why AI made it worse, and how it gets solved.
High Bandwidth Memory is the bottleneck of the AI buildout. Here is what HBM is, why it is in short supply in 2026, and the architectural alternatives.
Compute-in-memory performs calculations inside the memory that stores the data, eliminating data movement. Here is how it works, and how analog and digital CIM differ.
2.5D, 3D chiplets, and monolithic 3D all stack silicon — but at very different connection densities. Here is how they compare and why the distinction matters for AI.
Peak TFLOPS/W flatters chips that are starved for data. For real inference, energy per token — tokens per watt — is the number that decides datacenter cost.
The physics worked on 8 inches. Production meant making it boring on 12 — four matched chambers, 60 wafers an hour, no drama.
Two years after the 8-inch demonstrator, the production-scale 300 mm platform arrives: four chambers, 60 wafers per hour, BEOL-compatible growth.
Eighteen months after Prof. Chenming Hu's first check, the angel round closes — funding the 300 mm platform program and the Sophon architecture team.
Conventional MOCVD needs ~750 °C — hot enough to destroy a finished wafer. Here's how plasma and photons split that job between them.
First public demonstration of plasma-photon MOCVD: wafer-scale 2D TMD monolayers grown on 200 mm wafers at BEOL-compatible temperatures.
The father of the FinFET backs PhantaField's founding thesis: 2D semiconductors stacked into monolithic 3D are the path beyond silicon scaling.