PhantaField™ IP · PFG-1

SophonThe memory wall, demolished.

330 GB of DRAM living inside the compute array — not across a package, not on an interposer. 525× the weight bandwidth of any GPU. One die that trains and serves an 80B model.

64-tier monolithic stack — true scale0.35 µm tiers · 22.4 µm stack · drag to rotate
Logic / CIM2T0C DRAMSi CMOS BaseMIV Via

Every GPU ever built moves weights across a package to reach the math. Sophon puts the memory above the MAC — connected by a vertical via fabric with 10⁸ slots per square millimeter. The bottleneck doesn't get faster. It ceases to exist.

Architecture

Three Decisions, One Die

Sophon interleaves 32 logic tiers and 32 memory tiers in a monolithic 2D-TMD stack. Each DRAM cell sits directly above the MAC that consumes it — connected by sub-100 nm vias, not a bus.

01Memory

330 GB On-Die DRAM

  • 2T0C gain cell — 8 F², no capacitor, 1 fA/µm off-current
  • 1.8 s retention → refresh at 1 Hz (~0.08 W for 330 GB)
  • Holds 80B BF16 model + optimizer state + 10 GB activations
  • Fully writable: gradient accumulation at 20 fJ/bit
02Compute

Pure Digital CIM

  • 256×256 subarray per tile · binary sense amp + 8-level adder tree
  • Bit-serial activation at 500 MHz · 16 cycles BF16, 8 cycles FP8
  • 4,200 TFLOPS FP8 · 2,100 TFLOPS BF16 · 8,400 TOPS INT8
  • No analog conversion — deterministic, drift-free arithmetic
03Platform

2D-TMD Monolithic 3D

  • 28 nm Si CMOS base + 32 logic/memory doublets (64 tiers)
  • MIV vias at 90 nm pitch · 1.23 × 10⁸ slots/mm² · >99% headroom
  • BEOL growth ≤ 450 °C via NanoGalaxy PPMOCVD
  • ~22 µm total stack · single die serves training and inference
Specifications

Reference Design Metrics

PFG-1 reference configuration on a 750 mm² die. Architecture licensees may customize tier count, tile geometry, and memory density.

Benchmark

vs. NVIDIA B300 · Blackwell Ultra

B300 posts higher peak dense TFLOPS. But real inference at low batch is bandwidth-bound — and there, Sophon wins on every metric that governs actual throughput.

Weight bandwidth4.20 PB/svs 8.0 TB/s
525×
Decode throughput · 80B14,438 tokens/svs ~110 tokens/s
131×
Energy per token · 80B16.3 mJvs ~6,400 mJ
390×
Training throughput2,406 tokens/svs ~320 tokens/s
7.5×
TFLOPS per watt · BF163.72vs ~1.79
2.1×
Bill of materials$8,358vs ~$16,375
2.0×

Decode throughput modeled at batch 1, 80B parameters, FP8 mode (BF16-native decode is 7,219 tokens/s). B300 figures from published specifications and MLPerf-derived estimates.

Licensing

Integrate Sophon Into Your Silicon

Sophon is a licensable IP portfolio — not a standalone product. Choose the engagement model that fits your integration path.

AArchitecture License

Design & Integrate

License the Sophon RTL and memory controller IP for integration into your own SoC or multi-chip module. Includes full GDS-level reference design, memory timing models, and CIM tile generator.

BPlatform License

Co-Develop on PPMOCVD

License the full 2D-TMD M3D platform stack — process recipes, MIV via definitions, and 2T0C DRAM cell — for fabrication in your own fab or through our foundry partners.

CReference Silicon

Evaluation Samples

Receive tape-out samples of the PFG-1 Sophon die for benchmarking and software co-development before committing to volume production or full IP integration.

Get Started

License the architecture that ends the memory wall.

PhantaField partners with semiconductor companies, AI labs, and defense contractors for Sophon IP licensing and co-development. NDA-protected technology briefings on request.

  • RTL + GDS reference design delivery
  • Process integration support for PPMOCVD tooling
  • 96-tier variant — ~495 GB, full Adam optimizer — on the scaling roadmap