Project White Matter Whitepaper

WM-WP-001 · Packaging density as the path to bigger models · August 2026

AbstractThe largest AI model that can be trained or served is set by a physical property of the machine that hosts it: how much compute, memory, and bandwidth can act coherently — within one low-latency domain. This paper makes one argument with worked numbers: advanced high-density packaging raises that physical limit by roughly an order of magnitude. A conventional datacenter — racks of boards of organic packages — tops out near 1.5 trillion dense trainable parameters and one rack (~14 TB) of coherent memory, no matter how many racks are added. The White Matter brick — a hermetically bonded stack of liquid-cooled silicon interposer tiers with in-package power conversion and co-packaged optics, designed at its envelope's physical limit of 404 kW in 1.76 L (~230 kW/L) — lifts those limits to ~8 trillion dense parameters per gigawatt-site and petabyte-class coherent memory, at which point the binding constraints stop being the machine's and become the grid's, the fab's, and the optimizer's.

Keywords: high-density packaging · 3D interposer stack · model-size ceiling · coherence domain · communication-limited scaling · microchannel cooling · co-packaged optics

TRADITIONAL CEILING — ≈1.5 T DENSE · 14 TB COHERENT WHITE MATTER — ≈8 T DENSE · PB-CLASS COHERENT DENSITY 230 kW/L — DESIGNED AT THE PHYSICAL LIMIT BEYOND: GRID, FAB, DATA — NOT THE MACHINE

WM-WP-001 · August 2026 · Status: concept feasibility, sizing grade · Supersedes Rev B.16 (the broad-feasibility edition; its full subsystem analyses are preserved in the nine-application patent portfolio [1]) · All calculations shown inline; all assumptions stated where used.

#1The mission and the result

One mission: use advanced high-density packaging to push the trainable model size to a higher physical limit. Everything in this paper serves that sentence — the architecture exists to move one number, and the number is measured in trillions of parameters.

One rack becomes one box, drawn at true relative scale. At today's direct-liquid-cooled density, ≈120 kW of compute fills a rack (~1,500 L); the White Matter brick packages more than three racks' power in 1.76 L — ≈2,900× denser — by removing everything between the silicon and the system — boards, cables, connectors, and the rack itself. The rest of this paper develops how (4) and what the density buys (5–6).

The argument runs in four steps. Model size is capped by how much compute can act coherently, and coherence is capped by physical distance (2). In the traditional stack the coherent domain ends at the rack, which fixes its ceiling near 1.5 T dense parameters no matter how many racks a site adds (3). The brick packages compute ~2,900× denser and replaces the rack boundary with in-room fiber (4), which hands the ceiling to the site's power budget instead: ≈8 T per gigawatt, scaling as √power beyond, with petabyte-class coherent memory for 1,000 T-total mixture-of-experts (MoE) models (5). 6 puts the two ceilings side by side.

#2Why model size hits a physical wall

Training is communication-bound before it is compute-bound. A synchronous job divides its compute per step across N accelerators, but the communication floor does not divide — and that floor is set by physical distance, because every component of communication cost grows with it: latency (5 ns per metre of fiber, plus 0.3–1 µs per switch traversal that distance makes necessary), energy (~0.3 pJ/b on silicon → ~2 pJ/b over rack copper → 10–20 pJ/b over switched inter-rack optics), and bandwidth taper (fabrics thin their bisection 2–4× per tier because distance makes bandwidth expensive).

Worked numbers — the distance ladder

Tier	Distance	Latency / hop	Energy	Bisection
in-package (silicon + TSV)	mm–cm	1–3 ns	0.3–0.5 pJ/b	full
in-room, brick ↔ brick	1–15 m	5–75 ns — fiber, point-to-point	3–5 pJ/b	provisionable — no taper
rack ↔ rack (traditional)	10–200 m	1–5 µs — fiber + 2–4 switch traversals	10–20 pJ/b	tapered 2–4× per tier

Three ceilings then set the largest useful machine, and only one belongs to the algorithm:

The coherence ceiling — a replica's fast parallelism (tensor/expert) must live inside a sub-µs, Tb/s-class domain. Where that domain ends, the machine effectively ends: a decode step's ~200 collectives per token turn µs hops into ms of token latency, so serving never leaves the domain either.
The reliability ceiling — synchronous-job failure rate grows with component count; reported frontier practice holds synchronous domains near 2–5×10⁴ accelerators, dominated by cables, connectors, and optics.
The algorithmic ceiling — data parallelism stops converging faster past the optimizer's critical batch (~10⁷–10⁸ tokens), capping useful replicas near 10⁴. This one is architecture-independent; the mission is to push the first two ceilings up until this one binds.

Model size follows directly: for a compute-optimal dense run (tokens ≈ 20 × parameters, C = 120 P²), P_max = √(usable-job throughput × run time / 120) — and "usable-job throughput" is capped by the coherence and reliability ceilings, not by the site's nameplate power. Density is the lever because distance is the tax: pack the same compute smaller and the ladder's bottom rung disappears.

#3The traditional approach's physical limit

In the rack-of-PCBs-of-organic-packages stack, the coherent domain ends at the rack: 8–72 accelerators on copper, with everything beyond reached through switched optics at µs latency. Density cannot fix this from inside the paradigm — packing racks closer does not remove the rack boundary, because the boundary is architectural (board → cable → switch), not spatial. The consequences, quantified:

Worked numbers — the traditional ceiling

Quantity	Result	How
Coherent domain	one rack ≈ 14 TB	8–72 accelerators × 192 GB HBM ≈ 14 TB, on copper; everything beyond is reached through switched optics
Single-job knee	40–100 MW	~2–5×10⁴ accelerators — coherence + reliability, regardless of site size
A 1 GW site	283 m · 1.4 µs	~200 m hall → 283 m diagonal, one-way; only ≈4–10 % of the site can act as one machine
Dense trainable — 100-day, compute-optimal	≈1.3–1.5 T	3×10⁴ accel × 10¹⁵ FLOP/s eff × 8.64×10⁶ s = 2.6×10²⁶ FLOPs → P = √(C/120); ≈1.3 T for the air-cooled estate (same arithmetic at ≈2.3×10⁴ effective accelerators)
Coherent-memory ceiling — serving / MoE-total	~14 T params	int8, one rack of HBM

The defining property of this ceiling is that it does not move with investment: more racks add capacity (more jobs, more users), never capability (a bigger coherent model, a faster training run). A gigawatt spent on the traditional stack buys the same ~1.5 T ceiling as 100 MW does.

#4The White Matter brick — density that removes the wall

The White Matter architecture, first disclosed in 2020 [2][3], is a sealed brick: a hermetically bonded stack of 40 silicon interposer tiers, ~100×200 mm each at a 2.2 mm pitch, carrying heterogeneous chiplets — 404 kW in 1.76 L (~230 kW/L), designed at the envelope's physical limit. Each tier's 2.2 mm stack-up: a 0.7 mm DRIE channel die + a 0.7 mm capacitor cap die (the two-die interposer), a 0.7 mm chip layer — HVI and spine segment dies at full height, compute dies thinned to 0.2 mm under 0.5 mm of heat-conductive fill — and ≈0.1 mm of hybrid-bond planes. Its five external interfaces (coolant in/out, power in and ground, optical fiber) replace the hundreds of connectors of a rack-based equivalent. Four packaging technologies produce the density; each is summarized here with its verdict numbers, and each is fully specified, with claims, in the patent portfolio [1]:

Two-die microfluidic interposers. Each tier is a bonded pair: a deep-trench-capacitor cap die metal-sealed over a DRIE (deep-reactive-ion-etched) channel die, the bond metal running over every fin top — one process step forming the electrical interconnect, the hermetic liquid seal of every channel, and the fin thermal feed (fin efficiency ≈0.99). Channels run parallel to the structural TSV (through-silicon-via) dies and are fed laterally from side plenums. Verdict: laminar Nu ≈ 5 in a 200 µm channel gives h = Nu·k/D = 5 × 0.6 ÷ 200 µm = 15 kW/m²K, and the ≈3× fin-area enhancement — fin-top-fed fins at η = tanh(mL)/mL ≈ 0.99 — lifts it to h_eff ≈ 45 kW/m²K: a film rise of ΔT = q/h = 22 K per 100 W/cm², plus q·t/k ≈ 5 K through the 0.7 mm cap die. The inter-tier fill adds the tier above as a second cold face (R_up ≈ 0.5 mm ÷ 3 W/mK + film ≈ 7× R_down → ≈12 % of heat upward), so sustained die flux reaches ≈145 W/cm² on ordinary treated water — used in full at the design point.
A central TSV-in-silicon power spine with per-tier conversion. 140 V descends the stack's centre — 2,900 A (404 kW ÷ 140 V), but the vertical run is only 88 mm (forty 2.2 mm tiers; the plates are thick copper bus) and liquid-cooled, so the spine is its own 5 × 100 mm TSV strip down the tier's centre (500 mm², 2.5 % of tier area) whose ≈100 mm² of via copper (~20 % fill) carries it at R = ρL/A = 1.7×10⁻⁸ × 0.088 ÷ 100×10⁻⁶ ≈ 15 µΩ (20 °C copper; ≈18 µΩ hot — the spine is a supply–ground conductor pair, one column landing on each plate, closing the loop plate-to-plate) — with the current tapering tier by tier, a worst-tier loop drop of ≈0.07 V (0.05 %) and a pair loss of ≈165 W (0.04 %) — computed per column (≈50 mm², ≈30 µΩ) with the supply and ground legs in series — fattening the spine is nearly free. The TSVs take 140 V on qualified liners: at ≈280 V breakdown (thick-oxide liners), 140 V is a 0.5 derating for ten-year TDDB life and ≈1 MV/cm of working field — where 400 V through silicon would stress the same liners at ≈3 MV/cm, invite substrate leakage and bond-interface creepage, and put high voltage millimetres from water channels. So the building distributes 140 VDC straight to the frame's busbars and nothing converts in the rack at all — the frame is copper, not electronics, and no through-silicon via ever carries more than 140 V. Each tier then converts beside the spine (an inductor-free switched-capacitor ladder built from the tiers' own trench capacitors: a ladder puts only the per-step ~10–15 V across each flying capacitor, so the same low-voltage trenches serve at any input voltage: flying capacitance C = I/(f·ΔV) = 12.6 kA ÷ (30 MHz × 0.2 V) ≈ 2.1 mF per tier from 0.5–1 µF/mm² trenches; the only high-voltage passive is the 140 V input decap, ≈0.5 µF ≈ 150 mm² per tier; three ≈96.5–97.5 % stages (≈175:1 in total) compound to η ≈ 90–93 %; gate-drive and control make the wall-to-core factor ≈1.12), so the ~13 kA-class core rail (a conservative 10.1 kW ÷ 0.8 V; delivered core current ≈11 kA) exists only over millimetres. At the physical limit, conversion is the envelope's largest area tax — capacitors 0.21–0.42 mm²/W plus comparable switch area ≈ 0.78 mm²/W, more tier area than the compute it feeds.
Shoreline co-packaged optics. Expanded-beam silicon benches (Fig. 2; ±24 µm passive alignment via the lensed fiber enclosure of Fig. 3) give every tier 12.8 Tb/s of escape bandwidth; a reserved fraction forms point-to-point express links between any tier or brick pair — so worst-case cross-machine bandwidth is a provisioning decision, not a topology penalty.
Designed-in redundancy. Pre-stack burn-in through the bond pads, spare dies and two spare tiers in the forty, and a fabric that routes around failures lift effective assembly yield from 0.95⁴⁰ ≈ 13 % to >95 % — and make months-long jobs ride through faults instead of checkpoint-restarting.

Fig. 1 — One tier of the brick. All vertical columns are silicon support pillars threaded with copper TSVs (power thick and few in the centre spine; signals thin and many in the side supports). At each tier the spine hands power off through the interposer substrate itself: lateral routing in the silicon body — drawn meeting the spine at the tier's routing layer — carries 140 V out to the flanking GaN·SC converter dies, which drop it to core voltage in place. The side columns are the HVI — hermetic vertical interconnect: stacked tier over tier, they run unbroken from the bottom plate to the top plate, and at every tier boundary the interface is a hybrid bond — a dielectric-to-dielectric bond embedding a fine-pitch array of copper bond pins — that carries the tier-to-tier signals and power and, with its perimeter seal ring, forms the hermetic seal that closes the package — one bonded interface doing electrical, mechanical, and sealing duty. The cross-section draws the columns as they are built: each tier's spine and HVI segments are separate dies — hybrid-bonded onto the interposer's top surface below and to tier n+1 above (each pad row in a bond plane is a copper pin array, its pads sized and aligned one-to-one with the TSVs they continue) — while the interposer body's own TSVs continue the vertical path through the tier, so the columns are stacks of dies and vias, not monolithic pillars. The trench-capacitor band is interrupted around the power routing: capacitors and wiring share the top of the body but never the same area. In the space between each chiplet and the capacitors beneath it sits the interposer’s redistribution stack — a few levels of horizontal wiring separated by dielectric spacers and stitched together by vias, contacting the die’s pads above and the capacitor band below — which fans each chiplet’s signals laterally out to the HVI columns at both shorelines, so a die talks to its neighbours and to the tier above without ever leaving the interposer’s own top metal. The photonic TX/RX die at each shoreline sits on that same top metal, outboard of the HVI column: its 8 Gb/s lanes run in the redistribution stack under the column and fan across the tier’s top metal to the express port of every die-site router — the section shows only the nearest (path ①) — and into the column’s signal TSVs to reach the tiers above and below (path ②) — the paths Fig. 4 draws in plan. The interposer body is itself a two-die bond — capacitor cap die metal-sealed over the DRIE channel die — with channels running parallel to the structural dies and a heat-conductive, electrically insulating fill coupling die tops to the tier above. The stack-up totals a 2.2 mm tier pitch: 0.7 mm channel die + 0.7 mm cap die + a 0.7 mm chip layer (HVI and spine segments full height; compute dies thinned to 0.2 mm under 0.5 mm of fill) + ≈0.1 mm of bond planes — × 40 tiers = the 88 mm stack.

The shoreline optics are two parts. The first is the bench — each tier's optical engine:

2020 disclosure rendering: side elevation of the bench optical train — photonic chip, collimating lens, free-space isolator, focusing lens, and fiber — Fig. 2 — The optical bench. Light is generated *outside* the package by a remote, replaceable continuous-wave laser bank and arrives on fiber; on the bench it is collimated, passes through a free-space isolator sitting in the expanded beam (where alignment is forgiving), is refocused into waveguides, split, and modulated by data-driven ring resonators tuned against the coolant-stabilized temperature; modulated lanes leave through lithographically seated lenses as expanded beams. Input and output lanes are unfolded here for clarity — both share the tier's shoreline. Two shorelines × 16 lanes × 400 Gb/s-class ≈ 12.8 Tb/s per tier. The renderings are the 2020 disclosure's own drawings [2]: the lens–isolator–lens side elevation and the splitter-and-ring-modulator plan. Bench, isolator, and tuning claims in patent application 4 [1].

2020 disclosure rendering: plan view of the bench — input lens and isolator feeding a one-to-four splitter tree with ring modulators and output ports — Fig. 2 — The optical bench. Light is generated *outside* the package by a remote, replaceable continuous-wave laser bank and arrives on fiber; on the bench it is collimated, passes through a free-space isolator sitting in the expanded beam (where alignment is forgiving), is refocused into waveguides, split, and modulated by data-driven ring resonators tuned against the coolant-stabilized temperature; modulated lanes leave through lithographically seated lenses as expanded beams. Input and output lanes are unfolded here for clarity — both share the tier's shoreline. Two shorelines × 16 lanes × 400 Gb/s-class ≈ 12.8 Tb/s per tier. The renderings are the 2020 disclosure's own drawings [2]: the lens–isolator–lens side elevation and the splitter-and-ring-modulator plan. Bench, isolator, and tuning claims in patent application 4 [1].

What makes this optical connectivity assemblable at all is a tolerance trick, first drawn in the 2020 disclosure [2] — the fiber enclosure carries a lens at every bore:

2020 disclosure rendering: elevation of the enclosure block showing the lens row and conically tapered bore entries — Fig. 3 — The lensed fiber enclosure: alignment tolerance is engineered, not fought. The block is manufactured as a **stack of bonded fused-silica wafers** — a microlens array photolithographically formed on the bench-side face, the fiber bores and conical entries etched through the wafers behind it — with the two sides registered by **double-sided photolithography**, so lens-to-bore alignment is a mask-overlay quantity (µm-class), not a machining tolerance. Each fiber then registers at its lens focus by simple insertion; because the beam crossing the mate plane is ~10× the fiber mode, misalignment sensitivity falls by the same factor — ±24 µm lateral and ±14 arcmin suffice, within mask-overlay and pick-and-place tolerances, where bare-fiber coupling would demand ±1–2 µm active alignment per fiber. This one part is the enabling detail behind the shoreline benches of 4, the stack-level fiber bundle enclosure, and the blind-mate trunks of the room fabric (Fig. 11). The renderings below the schematic are from the 2020 disclosure itself [2] — the block with its conical entries and lens row, fibers dropped in through the tapers, and the assembled part; full bench, isolator, and enclosure claims in patent application 4 [1].

2020 disclosure rendering: elevation with fibers dropped through the tapered entries and seated at the lens row — Fig. 3 — The lensed fiber enclosure: alignment tolerance is engineered, not fought. The block is manufactured as a **stack of bonded fused-silica wafers** — a microlens array photolithographically formed on the bench-side face, the fiber bores and conical entries etched through the wafers behind it — with the two sides registered by **double-sided photolithography**, so lens-to-bore alignment is a mask-overlay quantity (µm-class), not a machining tolerance. Each fiber then registers at its lens focus by simple insertion; because the beam crossing the mate plane is ~10× the fiber mode, misalignment sensitivity falls by the same factor — ±24 µm lateral and ±14 arcmin suffice, within mask-overlay and pick-and-place tolerances, where bare-fiber coupling would demand ±1–2 µm active alignment per fiber. This one part is the enabling detail behind the shoreline benches of 4, the stack-level fiber bundle enclosure, and the blind-mate trunks of the room fabric (Fig. 11). The renderings below the schematic are from the 2020 disclosure itself [2] — the block with its conical entries and lens row, fibers dropped in through the tapers, and the assembled part; full bench, isolator, and enclosure claims in patent application 4 [1].

Behind both optical parts sits the electrical path that turns the bench's light into the mesh's wires — and it is short. Everything inside the brick runs as 8 Gb/s parallel lanes on TSVs and RDL, chosen so that no link at millimetre reach pays a SerDes; the fiber runs at 50–100 Gb/s per wavelength, so the bench strip is the one place in the brick where lanes are serialized. A 400 Gb/s-class fiber is fifty 8 Gb/s lanes; sixteen fibers per shoreline are 800 lanes, 1,600 per tier — on the interposer's 2 µm RDL that is 1.6 mm of strip edge per routing layer against a 100 mm shoreline, so the landing the HVI arrays already need (≈13 layers for 625,000 lanes) absorbs the optics without a layer of its own. From the strip the lanes land on the same redistribution stack that fans chiplet signals to the HVI columns (Fig. 1) and take two paths. Laterally, they fan across the tier's top metal to the express port of every die-site router (Fig. 8): 1,600 lanes over sixteen sites is 100 lanes — two fibers' worth — at each port. Vertically, they enter the adjacent 10 × 100 mm HVI array, so that a tier's thirty-two fibers serve traffic from any tier: this tier's own 12.8 Tb/s is ≈0.3 % of a boundary's 4.4 Pb/s sustained, and even if every fiber's traffic crossed the same tier gap, the whole brick's 512 Tb/s of escape would be ≈12 % of one boundary — a worst-case bound equal to the whole ~10–15 % sustained vertical utilization the arrays are provisioned for (Fig. 8), not a fraction of it. Bench to router is 10–20 mm of top metal, nanoseconds at the 0.3 pJ/b of the wires; the fiber link itself is the distance ladder's 3–5 pJ/b (Section 2).

Fig. 4 — From the shoreline into the mesh. One shoreline of one tier in plan: fibers arrive through the lensed enclosure of Fig. 3, the bench strip modulates and detects them and serializes between the 50–100 Gb/s wavelengths and the brick's 8 Gb/s parallel lanes, and the lanes land on the interposer's redistribution stack beside the HVI array. Path ① runs laterally over the top metal to the express port of every die-site router (Fig. 8); path ② turns into the HVI TSVs, so a tier's fibers carry traffic for any tier — the inset shows the vertical route. The strip's 800 lanes take 1.6 mm of edge per routing layer, a rounding error on the landing the HVI already needs; one tier's optical escape is 0.3 % of a tier boundary's sustained capacity. The wires are the paper's stated link budgets (Figs. 7 and 8); the fiber link is the distance ladder's 3–5 pJ/b.

Fig. 5 — The cooling architecture that pays for the density, across three tiers of the repeating stack. Metal hermetic seal rings and fin-top bond joints (copper bars) make one bond step serve as electrical interconnect, per-channel liquid seal, fin thermal feed, and the structural web that couples the 0.7 mm cap die to the fins and lets it hold coolant pressure with margin. Combined double-sided ceiling ≈145 W/cm² (film 22 K + cap-die conduction ≈5 K per 100 W/cm²; ≈12 % relieved upward through the 0.5 mm fill).

Density and coherence follow. The brick is designed at the envelope's physical limit: ≈10.1 kW per tier, 404 kW per brick — ~230 kW/L, ~2,900× a direct-liquid-cooled (DLC) rack — the operating point where the converter-area tax and the 145 W/cm² flux ceiling bind jointly — solve P × (100/145 + 0.78 mm²/W) = 14,850 mm² of usable tier (15,000 less the ≈150 mm² 140 V input decap) → 10.1 kW — and the channel velocity lands on the ≈3 m/s erosion line: flow ṁ = P/(c_p·ΔT) = 404 kW ÷ (4.19 kJ/kg·K × 25 K) → 232 L/min per brick (5.8 L/min per tier) at 30→55 °C; ≈3 m/s through ≈800 × (200 µm)² channels per tier; laminar ΔP = 32µLv/D² ≈ 1.1 bar (hot-film µ ≈ 0.45 mPa·s with the rectangular-duct friction correction) + manifolds ≈ 1.4 bar; T_j ≈ 55 °C outlet + ~29 K film + ~6 K cap-die conduction ≈ 90 °C. Nothing is held in reserve: every watt the physics permits is packaged. And because bricks connect through in-room fiber rather than switched hops, the coherent domain grows from one rack to one room: a gigawatt is ~2,475 bricks in ~7 m, ~35 ns across — with express optics making any brick pair effectively adjacent.

Fig. 6 — Where the physical limit comes from. Each tier's 20,000 mm² must hold three things: a fixed ≈5,150 mm² (two shoreline bench strips 2 × 100 × 8 mm = 1,600 on the narrow edges; the two 10 × 100 mm HVI TSV arrays = 2,000; the 5 × 100 mm power-spine strip = 500; seal ring and keep-outs ≈ 900; the 140 V input decap ≈ 150); compute silicon, whose area per watt is set by the 145 W/cm² flux ceiling of Fig. 5; and power conversion at ≈0.78 mm²/W — the tax that grows fastest. The budget fills at ≈10.1 kW per tier → 404 kW per brick ≈ 230 kW/L — where, not coincidentally, the coolant velocity also reaches the 3 m/s erosion line: thermal, electrical-area, and hydraulic limits bind together, which is what makes this a physical limit rather than a design choice. At the limit, conversion occupies more tier area than the compute it feeds (≈8,000 vs ≈7,000 mm²). The equation conservatively rates the whole compute footprint at the ceiling flux; the actual 72 × 125 W inventory averages ≈130 W/cm² over it, leaving local hot-spot headroom.

Fig. 7 — The coherence machinery. Paths ① and ② are wired; path ③ shares the vertical fabric and collapses under load; path ④ — provisionable express fiber — is what caps the worst case and extends coherence beyond one brick to the whole room. The rates are wire-count arithmetic, not aspirations: ① adjacent dies talk through the interposer's horizontal wire array: a ≈40 mm shared edge ÷ 2 µm RDL pitch × 4 routing layers = 80,000 wires × 8 Gb/s ≈ 640 Tb/s raw, ≈280 Tb/s sustained; ② the two 10 × 100 mm HVI TSV arrays thread ≈1.25 million signal TSVs through every tier boundary — × 8 Gb/s ≈ 10 Pb/s raw, ≈4.4 Pb/s sustained after direction and protocol overhead, ~270 Tb/s per die; ③ under full load ≈320 concurrent flows contend at the most-loaded of the 39 boundaries — 4,400 ÷ ~320 ≈ 14 Tb/s for a distant pair; ④ each express fiber carries 8–16 wavelengths × 50–100 Gb/s = 0.4–1.6 Tb/s. This is the mechanism by which density converts into a larger coherent machine, and hence a bigger model.

Fig. 7 parameters — the wired link budgets

Parameter	Value	Note
Same-tier wire array (path ①)	≈40 mm edge ÷ 2 µm pitch × 4 layers = 80,000 wires	horizontal RDL on the interposer between adjacent die sites
Same-tier bandwidth	80,000 × 8 Gb/s = 640 Tb/s raw → ≈280 Tb/s sustained	÷2 directions, ~13 % protocol; ≈190 W per edge at full saturation (0.3 pJ/b), duty-cycled by the workload
Signal-TSV pitch	40 µm	hybrid-bond-class vertical interconnect through the two HVI columns (the 5 × 100 mm centre spine carries power)
Signal TSVs per tier boundary	2 × (10 × 100 mm) ÷ (40 µm pitch)² → ≈1.25×10⁶	two 10 × 100 mm HVI arrays, 2 × 625,000 TSVs; array area 2,000 mm² = 10 % of the tier — committed by design
Lane rate per TSV	8 Gb/s	simple parallel signalling — no SerDes power tax at millimetre reach
Raw boundary bandwidth	1.25×10⁶ × 8 Gb/s ≈ 10 Pb/s
Sustained per boundary	≈4.4 Pb/s	÷2 for direction pairing, ~13 % protocol overhead
Per die, one hop (path ②)	≈78,000 TSVs/die → ≈270 Tb/s	16 die sites per tier — each a multi-chiplet package of ≈125 W chiplets (≈72 chiplets/tier)
Worst case, tier 1→40 loaded (path ③)	≈14 Tb/s	under full load ≈320 concurrent inter-tier flows contend at the most-loaded of the 39 boundaries: 4,400 ÷ ~320 ≈ 14 Tb/s
Link power at full load	≈3 kW per boundary	0.3 pJ/b × 10 Pb/s; near zero at idle — saturating all 39 boundaries at once (~120 kW) would rival the compute budget, so the array is sized for reach and sustained vertical utilization is provisioned at ~10–15 %
Binding constraint	escape routing	landing 625,000 lanes per array needs ≈13 routing layers on the 100 mm strip edge (100 mm ÷ 2 µm ≈ 50,000 lanes/layer) — the layer count the two-die 1.4 mm interposer's stacked RDL exists to provide

What turns these wires into an NVLink-class service — uniform, schedulable reach from any chiplet to any other — is a distributed router: one router block per die site, no central switch anywhere.

Fig. 8 — The distributed router: NVLink-class service without a switch die. Every die site carries an 8-port cut-through crossbar joining its two ≈280 Tb/s same-tier wire arrays, its ≈140 Tb/s cross-row array (the second Y port is a spare at the two-row edge), its ≈78,000-TSV shares of the tier boundaries above and below (≈270 Tb/s each — the 10 × 100 mm HVI arrays make the vertical direction no scarcer than the horizontal), its chiplets, and an express port into the shoreline optics — forming an 8×2×40 mesh per brick with fiber skip links beyond. Adaptive multi-path routing spreads flows across the mesh; virtual channels and QoS protect latency-critical traffic; and an in-fabric collective engine executes reductions and multicast at line rate, which is what training actually needs from uniformity. The any-pair injection floor is set by the vertical cut (≈4.4 Pb/s ÷ 72 chiplets per tier ≈ 60 Tb/s; under the full 320-flow contention of Fig. 7 a distant pair still holds ~14 Tb/s on wires, with express fiber capping the worst case), while adjacent-die traffic rides the 280 Tb/s arrays — wires reward locality, and the router makes the rest uniform. Extends the fabric-router claims of patent application 7 [1].

Fig. 9 — The brick in two engineering views. A, sectioned along the coolant axis: the supply plenum spans one wide face and the return plenum the opposite face, with all forty tiers' microchannel fields in parallel between them — coolant passes straight through in one direction, 30→55 °C at 232 L/min and ΔP ≈ 1.4 bar. B, the shoreline face: forty interposer-plus-die layers between the +140 V plate and the ground plate; the central spine and both HVI columns per-tier-segmented, their hybrid-bond pin interfaces (dashed) repeating at every boundary — the spine's two conductor columns forming a supply–return pair, one landing on the +140 V plate and the other on the ground plate, while the signal-carrying HVI columns run the full stack, separated from both plates by thin insulation gaps; and each tier's 16 fibers per shoreline leaving through the lensed enclosures (Fig. 3) — 640 per side, 12.8 Tb/s per tier. 100 × 200 × 88 mm = 1.76 L at 404 kW; everything the brick exchanges with the world crosses the five interfaces shown: coolant in/out, power in and ground, fiber.

assembled exploded auto cycle rotate drag to orbit · scroll to zoom

interposer tiers ×40 + die layers — true scale power plates · per-tier spine/HVI segments coolant in/out — straight through the wide faces fiber enclosures · microlens arrays · fibers enclosing case: walls

Fig. 10 — The brick in three dimensions (interactive: drag to orbit, slide to explode). From inside out (drawn at true scale — all forty 2.2 mm tiers of the 100 × 200 × 88 mm brick): forty interposer tiers — each carrying its chiplet grid (64 chiplets drawn per tier) — between the ground plate and the +140 V top plate, threaded by the central power spine and the two HVI columns — themselves stacked from per-tier segments that bond at every tier boundary, which is why each tier carries its own segments apart in the exploded view; the coolant path crossing the two wide faces — drawn as flow arrows passing straight through, in one face and out the opposite, exactly as the water moves — while the fiber enclosures sit on the two narrow faces — their inner faces carrying the microlens arrays of Fig. 3, one lens per fiber — their fiber bundles fanning out from every tier (drawn in real number: 16 fibers per shoreline per tier, 640 per side, one lens each); and the enclosing case walls, with the coolant in/out and the power and ground drawn as flow arrows: coolant passes straight through in one direction — in through one wide face, out the opposite — and power enters from above with ground below. What the case presents to the world is exactly the five interface classes of 4: coolant in/out, power in and ground, fiber.

The room fabric that carries this coherence is itself switchless — assembled from three passive part types, with no fiber handled in the field:

Fig. 11 — How bricks connect: the network is a bill of passive parts. Each shoreline's fibers leave the sealed brick as one factory-terminated trunk and blind-mate — expanded-beam, dust-tolerant — when the brick slides into its frame slot. A passive frame shuffle (an optical flex circuit, no electronics) re-sorts the frame's brick trunks into destination trunks: a full in-frame mesh plus trunk cables to every other frame. Bandwidth between any brick pair is then set by which fibers and wavelengths the endpoints light — never by a switch — so reprovisioning is software, replacement is slide-in, and the only field acts are blind-mating bricks and pulling trunks. Detailed in patent application 8 [1].

Between the brick and the room stands one mechanical part: the service frame — the thing that actually puts bricks on a datacenter floor. Each brick lives between the left and right halves of a hermetically sealed liquid-cooling case; its back face is a fiber panel, its top and bottom faces are its electrical connections. The frame does three jobs. It terminates the building's distribution — liquid and 140 VDC arrive from the top, fibers leave at the front and the back. It delivers power as copper, not electronics: the building's 140 VDC lands on a laminated busbar pair running the frame's full height beside each brick column, and each bay's electrodes clamp the busbar's supply lamina over the brick's top plate and its ground lamina under the bottom plate — ≈2,900 A per brick, with no conversion stage anywhere between the building bus and the spine. And it turns installation into a slide plus one panel: sliding the brick home engages the self-connecting liquid fittings and the back shoreline's fibers; attaching the front fiber panel finishes the bay.

seated withdrawn auto cycle rotate drag to orbit · scroll to zoom

bricks ×32 in sealed cooling cases — slider = service motion (bricks and their front panels + bundles come out the front; busbars, electrodes, and piping stay) 140 VDC laminated busbars (supply + ground) · per-bay electrodes top/bottom · ≈92 kA at the feed liquid pipes — central supply drop · DN40 branches + gap drops · side return pipes to the top fiber bundles — real count: 640/shoreline per brick · ≈80% rise to the inter-frame trunks (front + rear) · ≈20% cross-connect brick to brick inside the frame

Fig. 12 — The service frame: how bricks meet the datacenter floor. A: 32 bricks in two columns flank a central liquid-supply drop that runs from the top of the frame to the bottom; a per-bay branch feeds each brick's sealed cooling case, and the returns leave the case's left and right sides for the two outer risers and climb back to the top — liquid and power both arrive overhead, fibers leave at the front and the back, and the bottom two bays hold dark-fibered spares. Power is a pair of full-height 140 VDC laminated busbars (supply and ground laminae), one per brick column, each carrying ≈46 kA at the top feed and tapering toward zero at the bottom bay — a ≈110 × 260 mm bar section holding ≈13,000 mm² of copper per lamina (≈3.5 A/mm² at the feed, busbar practice for a cooled enclosure; ~1.1 t for the pair — the honest price of a frame with no power electronics in it). Each bay's electrodes reach from the busbar over the top plate and under the ground plate, and the ~50 mm service gap between busbar and cooling case carries the DN40 drop, so copper and pipe never share volume. B: the install sequence — ① the brick slides in, its cooling-case ports meeting self-connecting fittings inside the frame while the back fiber panel engages; ② the front fiber panel is attached, completing the bay — its 640-fiber bundle (drawn in real number, like the back one) travels with the panel. 32 × 404 kW = 12.9 MW per frame at ~7,400 L/min; ~4–5 t on slab (no raised floor — every service overhead); 77 frames plus spares tile a ~7 × 10 m floor. The interactive model below shows the frame in three dimensions — drag to orbit; the slider runs the service motion: each brick comes forward with its front panel and that panel's fiber bundle — the trunks paying out slack from their fixed ceiling penetrations — while the busbars, electrodes, piping, fittings, and back panels stay put.

#5The White Matter physical limit

With the rack boundary gone, run the same model-ceiling arithmetic on White Matter:

Worked numbers — the White Matter ceiling

Quantity	Result	How
Coherent domain	one room — ~7 m · ~35 ns	1 GW ≈ 2,475 bricks; express fibers join any brick pair point-to-point — no switch tier, no taper
Reliability	knee moves ~10×	≈140× fewer field connections per MW — a DLC rack ≈ 500 (40 nodes × coolant pair + power + optics) per ~120 kW ≈ 4,200/MW vs the brick's 12 (2 coolant + 2 power + 8 trunk ferrules) per 404 kW ≈ 30/MW — plus ride-through redundancy converting residual faults to non-events
Dense trainable — 100-day, coherent 1 GW ≈ 890 MW core	≈7.5–8 T	7.1×10⁶ dies × 1.25×10¹⁴ FLOP/s = 8.9×10²⁰ FLOP/s → C = 7.7×10²⁷ → P = √(C/120); ≈160 T tokens · 2.5×10⁶ steps · 3.4 s/step clears the critical-batch and in-room comm floors — the machine is no longer the binder
Coherent memory	PB-class — 10²–10³× a rack	quadrillion-parameter (1,000 T-total) MoE: 10¹⁵ params × 8–32 bytes of training state = 8–32 PB across 200–800 memory-weighted bricks (~40 TB class each); compute C ≈ 120 × (5 T active)² = 3×10²⁷ FLOPs ≈ 45–90 d at 0.5–1 GW; all-to-all ~200 Tb/s aggregate → ≲1 Tb/s per brick — ≪1 % of each brick's 512 Tb/s shoreline
Unlimited power — 100-day runs	8 T @ 1 GW · 25 T @ 10 GW 80 T @ 100 GW · ≈250 T @ 1 TW	P ∝ √(power × time); the next binders are the fab (10¹² W ÷ (125 W × 1.12 wall-to-core) ≈ 7.1×10⁹ chiplets per TW ≈ a decade of world logic output) and the dataset (D = 20 P: >10¹⁵ tokens must be synthesized); communication never re-binds (even a TW-scale room is <1 µs across); the serial-step wall (100-day calendar ÷ ~1 ms step floor = 8.6×10⁹ steps × 10⁸-token batches → D ≈ 10¹⁸ → P = D/20 ≈ 4×10¹⁶) sits orders of magnitude above the ladder and never binds

Restated: the brick pushes the hardware ceilings past the algorithm's — nothing that binds at its limit is a property of the machine, which is the most a packaging technology can achieve.

#6Head-to-head: the two physical limits

Physical limit	Traditional (rack + PCB + organic)	White Matter brick	Ratio
Deployed compute density	0.005–0.08 kW/L	230 kW/L — at the physical limit	≈3×10³–5×10⁴×
Coherent (fast) domain	one rack — 8–72 accel, ~14 TB	one room — ~2,475 bricks ≈ 7×10⁶ chiplets, PB-class	~100×
1 GW machine: diameter · latency	283 m · 1.4 µs	~7 m · ~35 ns	~40× · ~40×
Single-job knee	40–100 MW (≈4–10 % of site)	~the whole site	~10–25×
Dense trainable, 100-day run	≈1.3–1.5 T	≈8 T per GW	~5×, and √-scales with power
Total params (MoE) hostable coherently	~14 T	~1,000 T-class	~70×
What binds at the ceiling	the machine — rack boundary, cables	grid, fab, data, optimizer	—

How does this compare with the strongest announced version of the rack paradigm — NVIDIA's Vera Rubin generation [8]? Fairly, only at matched scale and with the asymmetries stated: Rubin is committed product with published specifications; White Matter is a concept at sizing grade that, being a packaging architecture, is assumed to host the same class of silicon. Two comparisons follow — unit against unit at the same power, then deployment against deployment at the same site power.

One unit against one unit (the brick draws ~3 racks' power)	Vera Rubin NVL72 rack (announced, 2026)	White Matter brick (concept)
Power · volume	~130 kW class · ~1,800 L	404 kW · 1.76 L
Silicon	72 Rubin GPUs (144 dies)	~2,880 chiplets in 640 die sites
Memory in the unit	72 × 288 GB HBM4 = 20.7 TB · 1.6 PB/s (22 TB/s per GPU)	~40 TB class, configuration-dependent — same-silicon assumption per chip
Chip-to-chip bandwidth	NVLink 6: 3.6 TB/s per GPU — switched, full rate to any of the 72	≈35 TB/s to each same-tier neighbor (interposer wire array) · ≈34 TB/s per die across a tier boundary (10 × 100 mm HVI arrays) + provisionable express fiber
— verdict on chips	for adjacent dies the interposer wire array is ~10× NVLink (advantage White Matter); and with the HVI arrays the vertical direction stops being scarce — uniform any-pair floor ≈60 Tb/s ≈ 7.5 TB/s per chiplet, ≈2× NVLink's 3.6 TB/s, with unit bisection ≈4.4 Pb/s vs ≈1 Pb/s (≈4×, at ~3× the power). NVLink's remaining edge is placement-independence: full rate to any of 72 large-HBM peers, where the brick's rates grade with distance
External connections	hundreds — cables, transceivers, quick-disconnects	five interface classes; blind-mate
Cooling	cold plates on packages	in-silicon microchannels, 145 W/cm²

One deployment, same site power (1 GW)	Vera Rubin estate	White Matter room
Units	≈7,700 NVL72 racks (≈1,700 at Kyber's 600 kW)	≈2,475 bricks in ≈77 frames
Building	hall class — 283–447 m spans (3, Fig. 13)	one ~7 m room
Largest coherent domain in the site	one rack — 20.7 TB HBM (365 TB fast memory by Kyber, 2027)	the whole site — PB-class
Between domains	switched, tapered fabric — µs hops	no boundary — point-to-point fiber, ~35 ns
Serving / MoE-total ceiling (int8, one domain)	~21 T in HBM → ~365 T (Kyber)	1,000 T+
Dense-training ceiling	~1.5 T-class knee at 40–100 MW (3)	≈8 T per GW, power-bound (5) — paper numbers

Read both directions — and note the convergence: NVIDIA's own framing of NVL72 is that a larger unified scale-up domain lets MoE expert parallelism and distributed KV cache run across the entire rack. That is precisely this paper's argument, one level down; White Matter extends it from a 72-GPU rack to a ~2,475-brick room. Rubin's strengths are real: committed silicon, chip-to-chip links that reach any rack peer at full rate, and an ≈18× coherent-memory roadmap by 2027 (20.7 → 365 TB). What no rack generation changes is the scale at which the domain ends and a switched fabric begins. Announced figures per NVIDIA [8]; NVL72 rack power as commonly reported; White Matter figures are this paper's sizing-grade derivations, shown inline where each number appears; unverified by hardware.

Fig. 13 — Density is the lever. Packing ≈2,900× denser (230 kW/L in the brick, ~15 kW/L at facility level after infrastructure) shrinks a 1 GW machine from a 283 m hall at 1.4 µs one-way to a 7 m room at 35 ns (halls: 10⁹ W ÷ 0.005–0.08 kW/L of estate → 447–283 m diagonals; room: 10⁹ ÷ 15 kW/L = 67 m³ ≈ a 4 m cube → ~7 m with access; latency = distance × 5 ns/m) — and because bricks connect by point-to-point fiber, that room is one coherent domain with no rack boundary. Fig. 14 shows what this buys in model size.

Fig. 14 — The two ceilings. Below the knee both stacks convert power to compute at similar efficiency, so the curves track together. At 40–100 MW the conventional ceiling goes flat: coherence and reliability cap the largest synchronous job at ≈1.5 T regardless of site size. The brick has no machine-bound knee — its ceiling follows √(power × time) through 8 T at 1 GW to ≈250 T at a terawatt (100-day runs), until fabrication capacity (each TW ≈ 7.1×10⁹ dies ≈ a decade of world logic output) and token supply (D = 20 P > 10¹⁵ tokens) bind — constraints that stand outside the machine. Class estimates per 3–5.

The comparison read plainly: the traditional stack's ceiling is a property of its packaging — the rack boundary — and is therefore fixed no matter the investment. The White Matter ceiling is a property of everything except the packaging: grid power, fab output, token supply, and the optimizer. Moving the ceiling from the first category to the second is the entire mission, accomplished at roughly 5× on dense trainable size (√-scaling beyond with power), ~70× on coherent total parameters, and ~40× on synchronous-domain latency.

#7The payload case for orbit

Orbit is proposed for the same reason 5 and 6 were written: once packaging stops binding the machine, what remains is the environment — near-continuous solar power, at the cost of the eclipse storage priced below, and no land or interconnect queue. The public record is thin against the ambition. Flown: one H100 on Starcloud-1 (60 kg, November 2025) [9], two Axiom nodes on Kepler relay satellites since January 2026 [10], and China's twelve-satellite Three-Body Computing Constellation, which has run an 8-billion-parameter model on orbit and held a 192-hour optical inter-satellite link [11]. Bench and paper: Google's Project Suncatcher, whose most useful contribution is a Trillium TPU in a 67 MeV proton beam showing no hard TID failure to 15 krad(Si) against an expected shielded five-year LEO dose of ~750 rad(Si) [12]. Filed: SpaceX's million-satellite application [13], Blue Origin's 51,600-satellite Project Sunrise [14]. Six orders of magnitude separate the largest single accelerator operating — ~700 W — from the largest constellation announced. This paper can answer only the question its own subject bears on, and in orbit that question has one currency: every claim reduces to kilograms lifted.

Start with what the architecture puts on the manifest. A brick is 1.76 L and ≈6.25 kg — 1.76 L of near-solid silicon is 4.10 kg, so a 40-tier stack cannot be far from 4.29 kg whatever the composition argument, plus ~1.96 kg of case, copper plates and optics — so a gigawatt of compute is 15.5 t, or 363 t once its frames and busbars are counted — 77 frames at ~3.4 t of terrestrial, gravity-loaded structure, plus ~87 t of busbar copper set by 92 kA per frame at 140 VDC and 3.5 A/mm² on a tapered-distribution model, where an untapered round trip would multiply that copper several-fold. The conventional equivalent is 7,692 racks at 130 kW, ~1,350 kg and ~1,500 L — 10,384 t — a counterfactual worth naming as such, since no orbital proposal actually launches datacenter racks; it is retained because it is the one mass-audited reference that exists. The tempting ratio is 671× and it is not apples-to-apples, since the rack figure already contains chassis, in-rack busbar and cold plates; charge this machine's own frames and busbars against them and the honest number is ≈29× — an upper bound, since the 363 t omits the external laser bank, the room's optical shuffles and the coolant distribution. As a hardware figure of merit — compute mass only, and not yet the number that decides anything — the brick is 3.60×10¹⁷ FLOP/s in 6.25 kg, or 5.76×10¹⁶ FLOP/s per kilogram.

Kilograms become flights. On a 125 t / 1,000 m³ vehicle the break-even payload density is 125 kg/m³; racks stow at ~900 kg/m³ and are therefore mass-limited by 7.2×, so a gigawatt of them demands 84 dedicated flights — 81 on a net basis, after the frames and busbars this machine flies in their place. Deleting 10,021 t net is worth $2.0 B at a $200/kg threshold price — the figure orbital-datacenter proposals commonly assume, and one no vehicle has demonstrated — $0.50 B if launch ever reaches $50/kg, and $10.0 B at today's ~$1,000/kg — against a silicon build cost of $1.4–14 B (7.13×10⁶ chiplets at $200–2,000 each). That is the saving, stated at its largest defensible size. The only flown orbital datapoint says the same thing from the other side, and more fairly: Starcloud-1 put one 700 W accelerator in orbit for 60 kg of spacecraft [9] — 86 kg/kW, bus included — against this machine's 24 kg/kW for the entire gigawatt manifest below. Whole system against whole system, the advantage is a factor of about 3.6, not 671.

Now the context that decides how much it is worth. The rest of the manifest, per gigawatt: ~1.4 km² of radiator — Stefan–Boltzmann at a 42 °C effective radiating temperature, ε ≈ 0.885, both faces, ×1.2–1.3 for fin efficiency and blockage — at 3–14 kg/m², deployable-panel demonstrators to flown ISS assemblies [16] (4,200–19,600 t); ~3.2 km² of photovoltaics at ~320 W/m², sized to ~1.03 GW of array at 100–200 W/kg (5,150–10,300 t); ~360 MWh of eclipse-season storage at 150–250 Wh/kg plus the ~29 % of extra array (~0.9 km²) needed to recharge it (2,900–5,400 t, plausibly double once ~7,500 eclipse cycles over five years are derated for usable depth of discharge); the transport loop (1,000–5,000 t); and drag makeup (200–400 t at moderate solar activity, assuming electric propulsion at ~2,000 s specific impulse). Taking the radiator at a 7 kg/m² centre, the array at 150 W/kg, storage at 200 Wh/kg and the loop at 3,000 t gives a non-compute manifest of 23,758 t = 191 flights, leaving 117 t of rounding remainder — so the 15.5 t of compute adds zero flights, and the full 363 t adds two out of 193. The result is real but it is not robust: 125 t is a nominal LEO figure, a 550 km dawn–dusk orbit plausibly cuts it to 80–110 t, and while the zero-flight answer survives at 100 t it fails at 80 t, where the remainder closes to 2 t and the compute costs a flight of its own. It is also smaller than the term it sits inside: payload adapter and dispenser structure at a normal 3–8 % of payload mass is 716–1,910 t across the campaign, two to five times the entire 363 t under discussion.

Fig. 15 — What a gigawatt lifts. The per-gigawatt launch manifest at the centre case — radiator at 7 kg/m², array at 150 W/kg, storage at 200 Wh/kg, transport loop 3,000 t, drag makeup 300 t. Below the dashed line sits the 23,758 t that packaging cannot touch, identical in both columns because radiator area follows from Stefan–Boltzmann and that expression contains no density term. Above it is the only thing packaging changes: 363 t of compute, frames and busbars against 10,384 t of racks — a saving of 10,021 t and 81 of 274 flights, ≈$2.0 B at a $200/kg launch price. The compute block is drawn at true scale, which is the figure's whole point: at 1.5 % of its own column it is the smallest item on the manifest, and everything the orbital case turns on is carried by the two blocks beneath it.

Two reversals have to be stated here, because both cut against the reading this paper would prefer; a third belongs to the thermal case this section does not reopen. The saving is a mass story and not at all a density story. 4.36 m³ of brick per gigawatt against 11,538 m³ of racks is a volumetric advantage of the same ≈2,900× order — that buys nothing at the pad: both are mass-limited, and both fly with the fairing 85–96 % empty. And the same holds for the largest line on the manifest — the radiator follows from Stefan–Boltzmann, whose expression contains no length, no volume and no density term, so a 230 kW/L brick and a 0.08 kW/L rack rejecting the same gigawatt at the same temperature need identical panels. The second reversal is sharper: measured against everything that has to be lifted, the orbital machine delivers 37 TFLOP/s per kilogram launched — 2.3× worse per kilogram than the same silicon sitting on a datacenter floor, and only 1.42× better than that manifest flying racks instead. A payload argument that stops at 671× is not an argument; the honest one is 29× on hardware, 81 flights, and roughly $2.0 B.

Three second-order payload items are worth naming, and one of them inverts. Power distribution is DC-native, so a solar-array bus meets 140 VDC busbars with no inverter stage, where a terrestrial site has AC/DC, UPS and PDU to launch — but “copper, not electronics” is exactly backwards when mass is the cost function, and one would gladly pay conversion losses to raise the bus voltage and shed the 87 t of copper, except that 140 V was forced by the ~280 V TSV liner breakdown limit at a 0.5 derating for ten-year life. Shielding goes the right way and does not matter: 88 mm through the tiers is ~21 g/cm² of silicon, ~31 counting the case against the ~0.68 g/cm² of aluminium behind which that reference dose is quoted, and enclosing area collapses with unit surface — 230 m² per gigawatt against ~72,000 m² for a rack estate, or ~1.6 t of shield against ~490 t — but 1.6 t inside a 24,100 t manifest is noise, so TID self-shielding is a non-problem rather than a reason to fly — and it does nothing for single-event upset, which is untouched by shielding and scales with installed bits. The item that does carry weight is structural: every announced rival is a formation of free-flyers — Suncatcher's illustrative 81 satellites at 100–200 m spacing [12] — and each free-flyer pays for its own bus in structure, propulsion, attitude control and comms, on top of acquisition, pointing, tracking and formation-keeping against differential drag. A rigid 7 m structure at ~35 ns amortizes one bus across the whole machine — though these are design-point figures: an orbit-optimised machine that trades die flux for rejection temperature runs nearer ~243 kW per brick and ~4,120 bricks per gigawatt, ~25.7 t of compute in an ≈8.3 m room at ≈42 ns. The mass bound on that is small and should be said: the deployables need their own structure and attitude control whichever way the compute is packaged, so consolidation reaches only the compute core — 363 t of a 24,100 t manifest. What it really saves is the pointing, tracking and formation-keeping a rigid machine never performs, which is a complexity argument rather than a payload one. It is also conditional, and the condition is severe: a 1.4 km² panel cannot be packed around a 7 m room without the panels shading one another, so either the loop grows to a kilometre and 1,000–5,000 t, or the machine spreads to feed its panels and the formation comes back. And nothing 7 m across flies in a fairing, so all of it presumes on-orbit assembly — which is what the Horizon Europe ASCEND study concluded was a precondition [15].

Beyond the gigawatt site the ordering changes, and it is worth being exact about where. The compute-mass advantage binds wherever heat rejection is somebody else's problem: bolted to a host platform with existing thermal margin, the marginal cost of compute is mass and volume alone and the ratio holds at 30–200× per kilowatt — an estimated ~0.05–0.09 kg/kW for a brick-based payload, mounting included, against 3–10 for conventional accelerator hardware — though the prize is only 3–250 kg across 1–25 kW of available margin. Duty-cycling helps less than it looks: the stack has almost no thermal inertia — the ≈65 J/K per tier of 8 is a ~130 ms dry-stack bound, and ~3.8 kJ/K counting the coolant standing in the channels gives 141–328 ms — so parity needs both a duty cycle under 0.08–0.37 % on the bare-compute basis, or 1.9–8.6 % once frames and busbars are counted, and a host structure or thermal capacitor willing to absorb the burst. On volume-constrained vehicles the advantage is absent outright: a 1–25 kW budget buys 4–110 mL of brick, and saving a hundred litres in a 10 m³ cabin is not an argument. Nor does the unit divide freely — the spine, the plate electrodes, the HVI columns and the 140 V feed are full-stack structures, so a partial stack is a redesign rather than a configuration.

What a payload argument cannot reach is the rest of the case, and it should be said plainly rather than listed rather than left as an omission.

No depot. The single-tier rework of Fig. 16 becomes downmass or scrap, provisioned redundancy becomes a consumable, and the water chemistry control that risk item (2) of 8 leans on has no orbital implementation at all.
Latchup is unmitigated. A single-event latchup path in a 125 W chiplet sits millimetres from the ~13 kA-class core rail of 4, with no stated per-die-site detect-and-cycle authority, and inside a sealed brick it is permanent.
Fluid in vacuum. 2 of the brick's 12 field connections are wet, so a gigawatt carries 4,950 fluid disconnects that in orbit would be welded — deleting the blind-mate model the service frame exists to provide.
Nothing guards the cold end. There is a <100 ms interlock against overheating and no protection at all against freezing; ice in 200 µm channels is destructive and irreversible, and survival heaters need the very power whose loss caused the problem. That is a new interlock and it is not written.
The downlink binds. 512 Tb/s per brick means even 0.1 % egress wants ~1.27 Pb/s to ground. That confines the workload to training and batch: a 100-day run uploading ~640 TB once for 160 T tokens fits; anything with an Earth-side dependency in the inner loop does not.

The judgement, stated as payload. What this architecture saves is 10,021 t and 81 flights per gigawatt — roughly $2.0 B at the launch price at which orbit is argued to make sense — and a compute mass that costs no extra flight at a 125 t payload, though it costs one at 80 t — and riding a remainder means sharing a fairing, a centre-of-gravity envelope and a separation sequence with a deployable, which is a different integration flow rather than spare capacity in the same one. What it does not save is the campaign: 13,400–40,700 t of radiator, array, storage, plumbing and drag makeup are untouched by packaging, and the 15.5 t of compute it does fly is 0.04–0.11 % of that. Orbit is therefore a decision about the price of lifting a power plant and a radiator, not about the density of the machine between them — and measured against everything that has to be lifted, this paper's contribution is a 1.42× payload advantage, not a 671× one.

#8Feasibility basis and risks

Every density claim above traces to a closed engineering budget — thermal, electrical, optical, hydraulic, yield — developed in full in the Rev B analyses and preserved, with claims, in the nine-application patent portfolio [1]. Beyond the figures already given in 4, the budgets close with 1–4 dB of optical link margin on a 50G-class link, a staged loss-of-coolant interlock (adiabatic heating dT/dt = 10.1 kW ÷ ≈65 J/K of tier thermal mass ≈ 140–170 K/s → a 20 K budget gives a ~115–140 ms window: first shed <50 ms, full shed <100 ms), and ~2–3 % cooling overhead on the chiller-free warm-water loop (pump ΔP·Q/η ≈ 1.2 kW per brick, ~0.3 %, + dry-cooler fans at 1.5–2.5 % of heat).

The bonded stack is also serviceable — permanent bonding does not mean permanent failure. When a fault exceeds the built-in redundancy, a depot fixture opens the housing, partitions the brick's coolant plenums into per-tier fluid circuits, and uses the stack's own microchannels to impose the temperature ladder of Fig. 16: only the two joints bounding the failed tier reach reflow, the sub-stack above lifts as one bonded unit, and a pre-tested replacement tier is re-bonded by the same per-interface heaters that released it — recovering the brick — 39 of its 40 tiers, ~97 % of its silicon value — rather than scrapping it [1].

Fig. 16 — Depot rework of a single tier. Left: comb manifolds partition the brick's own coolant plenums into per-tier fluid circuits, so the stack's microchannels — the same ones that cool it in service — impose the temperature ladder with full authority; only the two joints bounding the failed tier reach the Au-Sn reflow point, every other interface staying ≥100 K colder (the conduction leak through the fill, k·ΔT/t = 3 × 130 K ÷ 0.5 mm ≈ 78 W/cm², is absorbed by the neighbor tier's channels at ≈17 K film rise). Right: the upper sub-stack lifts as one bonded unit and a pre-tested replacement is re-bonded by the same per-interface heaters that released the joints. Full fixture, process, and design-for-rework features in patent application 9 [1].

The honest risk register, in order: (1) manufacturing maturity — thermocompression bonding of populated 200 mm tiers with ±10 µm height variation is the gating process demonstration; (2) the design carries no derating margin by construction — channel velocity on the 3 m/s erosion line, die flux at the 145 W/cm² ceiling, T_j ≈ 90 °C — so reliability comes from water chemistry control, the <100 ms interlock, and provisioned redundancy rather than headroom, and long-duration erosion–corrosion qualification is a gating test; (3) no prior-art search has ever been conducted on the 2020 disclosure or the 2026 refinements — required before any filing or investment thesis; (4) the MoE path's open item is algorithmic (expert routing at ~200× sparsity), not physical; (5) all figures here are sizing-grade class estimates — CFD, link measurements, and bond qualification will move individual numbers, but the order-of-magnitude ceiling comparison of 6 is robust to them; and (6) the orbital case of 7 presumes on-orbit assembly, has no depot and no coolant chemistry control, and leaves single-event latchup unmitigated.

Abbreviations and symbols AI — artificial intelligence · Au-Sn — gold–tin eutectic solder · CFD — computational fluid dynamics · decap — decoupling capacitor · DLC — direct liquid cooling (cold plates on racked servers) · DRIE — deep reactive-ion etching, the process that carves the microchannels · FLOP/s — floating-point operations per second · GaN·SC — gallium-nitride switches driving the inductor-free switched-capacitor network (the power-converter dies) · HBM — high-bandwidth memory · He — helium (leak testing) · HVI — hermetic vertical interconnect (Fig. 1) · h_eff — effective convective heat-transfer coefficient · IMT — Innovative Micro Technology, where the 2020 disclosure originated · MoE — mixture of experts, a model whose total parameters far exceed those active per token · PB / TB — petabyte / terabyte · PCB — printed circuit board · q↑ / q↓ — heat flux, upward / downward · T (as in "8 T") — trillions of model parameters · T_j — junction (die) temperature · TSV — through-silicon via, a copper conductor passing vertically through a silicon body · TX / RX — optical transmitter / receiver · UCIe — Universal Chiplet Interconnect Express · VDC — volts, direct current · 50G — 50 Gb/s-class optical lane · scaling symbols: P — model parameters, D — training tokens (D ≈ 20 P), C — training compute in FLOPs (C ≈ 120 P²) · units: kW/L — kilowatts per litre of hardware volume · W/cm² — heat flux per unit die area · Tb/s — terabits per second · pJ/b — picojoules per bit of data moved · ΔP — coolant pressure drop · MW / GW / TW — mega-, giga-, terawatt.

#References

Project White Matter patent portfolio, applications 1–9 (this repository, `patent/`): two-die microfluidic interposer; central TSV power spine with switched-capacitor conversion; conductive inter-tier fill; expanded-beam optical bench; the sealed compute assembly; assembly/test/redundancy; bandwidth-hierarchy fabric with optical express; switchless room-scale optical interconnect; single-tier rework fixture and process.
X. Xie and C. Gudeman, "3D liquid-cooled electrical optical interposer," IMT invention disclosure, June 2020 (project files).
Project White Matter pitch deck and elevation drawings, IMT, 2020 (project files).
D. B. Tuckerman and R. F. W. Pease, "High-performance heat sinking for VLSI," IEEE Electron Device Letters, vol. EDL-2, no. 5, 1981.
UCIe Consortium, Universal Chiplet Interconnect Express specification, 2022 onward — die-to-die bandwidth-density classes.
Public frontier-training practice reports and wafer-scale system materials — the observed 2–5×10⁴-accelerator synchronous-domain knee and spare-resource redundancy precedent.
WM-WP-001 Rev B.16 (superseded) — the full subsystem feasibility edition: power delivery, cooling, optics, interconnect, power and cost ledgers, benchmarks, and market analysis.
NVIDIA Vera Rubin platform disclosures: Rubin GPU 288 GB HBM4 at 22 TB/s, NVLink 6 at 3.6 TB/s per GPU, NVL72 rack-scale domain (technical-press summary supplied by the author, 2026); Rubin Ultra NVL576 (Kyber) figures per the GTC 2025 keynote as widely reported.
Starcloud (formerly Lumen Orbit) Starcloud-1 mission materials, November 2025 — a 60 kg satellite carrying an NVIDIA H100, reported nanoGPT training and Gemma inference on orbit; and the company's 88,000-satellite constellation filing.
Axiom Space — two orbital data center nodes deployed on Kepler Communications relay satellites, 11 January 2026 (company announcements).
ADA Space / Zhejiang Lab "Three-Body Computing Constellation" mission reports, May 2025 onward — twelve satellites, an 8-billion-parameter model run on orbit, and a 192-hour continuous optical inter-satellite link at 1,000 km.
Google Research, Project Suncatcher technical report, 2025 — Trillium TPU 67 MeV proton irradiation results (HBM irregularities near 2 krad(Si), no hard TID failure to 15 krad(Si)), bench optical link at 800 Gb/s each way, and the illustrative 81-satellite constellation at 100–200 m spacing.
SpaceX application to the U.S. Federal Communications Commission for a next-generation constellation of up to one million satellites, filed 30 January 2026.
Blue Origin, Project Sunrise — 51,600-satellite constellation filing and public technical framing, including a ten-to-twenty-year framing for gigawatt scale, 2026.
Thales Alenia Space, ASCEND — Advanced Space Cloud for European Net zero emission and Data sovereignty, Horizon Europe feasibility study, final reporting 2024.
NASA International Space Station Active Thermal Control System documentation — heat-rejection-system radiator ORU mass and deployed area (~1,100 kg over ~80 m²), used here as the flight-heritage areal-density anchor.

Limits of this analysis All numbers are sizing-grade class estimates from first-order models, computed inline with their assumptions. The single claim this paper defends is the comparison of 6 — a machine-bound ceiling near 1.5 T versus an environment-bound ceiling near 8 T per GW — and that order-of-magnitude gap survives any plausible refinement of the individual figures.