For two years the AI industry has been told the same thing: the next model needs more memory, and more memory means more HBM. But HBM is the one component the entire frontier is fighting over. Supply is locked up years in advance, prices have climbed faster than any logic node, and a single accelerator now spends more of its bill of materials on memory than on the silicon that does the math. PhantaField today introduced Sophon, a licensable AI architecture that answers the memory wall by refusing to participate in that market at all.
Sophon grows its memory directly above its compute. The PFG-1 reference design stacks 64 tiers of 2D transition-metal-dichalcogenide transistors on a mature 28 nm silicon base — 32 logic tiers interleaved with 32 memory tiers — and embeds 330 GB of capacitor-less 2T0C DRAM inside a pure-digital compute-in-memory array. Because every weight sits a few hundred nanometers above the multiply-accumulate unit that consumes it, the die delivers 4.2 PB/s of in-tile weight bandwidth: roughly 525× an eight-stack HBM3e package, at a bill of materials near $8,400 — about seven times below a comparable B300-class module.
One die that trains and serves
Capacity is the half SRAM accelerators cannot match. Where wafer-scale and chiplet designs hold megabytes to tens of gigabytes on-chip and must shard a single model across hundreds of devices, Sophon fits an entire 80-billion-parameter model — weights, optimizer state, and activation headroom — on one die. The same silicon trains in BF16 and serves low-batch inference at the compute-bound rate, so a fleet can be elastically repartitioned between training and serving without touching the hardware. At batch one it decodes that 80B model at 14,438 tokens per second in FP8, at 16.3 millijoules per token — roughly 390× less energy than an HBM-bound GPU spends at the same point.
The bottleneck doesn't get faster. It ceases to exist.
PFG-1 Whitepaper, §1
Three ways to build on it
Sophon ships as IP, not as a finished part. Customers can take an architecture license — the Sophon RTL, memory-controller IP, and CIM tile generator for integration into their own SoC; a platform license — the full 2D-TMD monolithic-3D process stack, MIV via definitions, and 2T0C cell, fabricated on NanoGalaxy PPMOCVD tooling or through foundry partners; or reference silicon — tape-out samples of the PFG-1 die for benchmarking and software co-development before committing to volume.
The complete technical case — cell physics, the digital CIM tile model, thermal analysis, yield, and a full economic comparison against Blackwell-class systems — is published in the PFG-1 whitepaper, Revision 4.1. Partners can request an NDA-protected briefing through the contact form.