As transistor scaling slows, the industry has turned to stacking silicon vertically to keep gaining density and bandwidth. Three approaches dominate the conversation — 2.5D, 3D chiplets, and monolithic 3D — and although they are often lumped together as packaging, they differ by orders of magnitude in how tightly they connect the layers. That connection density is the whole story.

Three ways to stack silicon: 2.5D, 3D chiplets, and monolithic 3D Three flat chip cross-sections compared side by side. 2.5D shows two dies side by side on a wide interposer slab with sparse vertical links, about 10 cubed links per square millimeter. 3D chiplets shows two dies stacked vertically with a row of bond bumps, micron pitch. Monolithic 3D shows a stack of six thin alternating logic and memory tiers threaded by many dense vertical vias, grown at 90 nanometer pitch with over 10 to the 8th slots per square millimeter, far denser than the others. THREE WAYS TO STACK SILICON 2.5D DIE DIE INTERPOSER ~10³ links / mm² SIDE BY SIDE 3D CHIPLETS DIE DIE bonded · µm pitch STACKED MONOLITHIC 3D LOGIC MEMORY VIA grown · 90 nm pitch >10⁸ slots / mm²
From side-by-side interposers to grown tiers, vertical connection density jumps five orders of magnitude — monolithic 3D wins on slots per mm².

2.5D integration

In 2.5D, separate dies are placed side by side on top of a silicon interposer — a passive slab of wiring that routes signals between them. HBM is attached this way. It is mature and reliable, but the dies remain in the same plane, connected through thousands of interposer wires per square millimeter. That is enough for chip-to-chip links, but far from the density needed to fuse memory into compute.

3D stacking and chiplets

True 3D stacking bonds finished dies on top of each other, face to face, using hybrid bonding — direct copper-to-copper contacts formed at the wafer surface. This is how stacked cache and some HBM-to-logic links are built. Connection pitch improves to the single-digit micron range, a big step up from 2.5D, but it is still limited by the mechanical reality of aligning and bonding two separately manufactured wafers.

Monolithic 3D (M3D)

Monolithic 3D is different in kind, not just degree. Instead of bonding two finished wafers, each new device layer is fabricated — grown — directly on top of the previous one, with no bonding step at all. Because the layers are built in place, the vertical vias connecting them can be as small as the lithography allows: PhantaField's Sophon uses monolithic inter-tier vias on a 90 nm pitch, which works out to over 100 million connection slots per square millimeter — roughly four to five orders of magnitude denser than 2.5D. That density is what makes it possible to put a memory cell directly above the compute unit that reads it, and to treat the whole 64-tier stack as one device rather than a package of parts.

Chiplets bond chips together. Monolithic 3D grows one chip in three dimensions.

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Frequently asked questions

What is the difference between monolithic 3D and chiplets?
Chiplets are separately manufactured dies bonded together, typically face to face with hybrid bonding at single-digit micron pitch. Monolithic 3D grows each device layer directly on top of the last with no bonding, allowing vias at sub-100 nm pitch — orders of magnitude denser.
What is 2.5D integration?
2.5D places multiple dies side by side on a silicon interposer that routes signals between them. HBM is attached this way. The dies stay in the same plane and connect through thousands of interposer wires per square millimeter.
Why does connection density matter?
The denser the vertical connections, the more tightly memory and compute can be fused. At monolithic-3D densities — over 100 million slots per square millimeter — a memory cell can sit directly above the compute unit that uses it, removing the data-movement bottleneck.
Is monolithic 3D the same as 3D NAND or stacked DRAM?
No. 3D NAND stacks memory cells of one type. Monolithic 3D stacks heterogeneous device layers — logic and memory together — each grown on the one below, enabling a single die that both computes and stores.